Semiconductor device with pre-molding chip bonding

Patent metadata

Field	Value
Publication number	US-9659885-B2
Application number	US-201414493718-A
Country	US
Kind code	B2
Filing date	Sep 23, 2014
Priority date	Aug 29, 2012
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a carrier layer;
a substantially flat bonding layer having a material reactivity of less than approximately one percent;
a debondable adhesive layer positioned between the carrier layer and the bonding layer, the carrier layer and the bonding layer being adhesively coupled to the adhesive layer; and
a chip comprising an electrical contact buried into the bonding layer.

2. The semiconductor device of claim 1 , wherein the adhesive layer is configured to release the carrier layer with respect to the bonding layer upon the adhesive layer being debonded.

3. The semiconductor device of claim 2 , wherein the debondable adhesive layer comprises one of a thermo-releasable adhesive and an ultra-violet-releasable adhesive configured to debond upon application of at least one of heat and ultra-violet energy.

4. The semiconductor device of claim 1 , wherein the chip comprises a plurality of electrical contacts each having approximately two (2) micrometers of separation between one another.

5. The semiconductor device of claim 1 , wherein the bonding layer is a polyamide epoxy.

6. A semiconductor device, comprising:
a carrier layer;
a substantially flat bonding layer having a material reactivity of less than approximately one percent;
a debondable adhesive layer positioned between the carrier layer and the bonding layer, the carrier layer and the bonding layer being adhesively coupled to the adhesive layer;
a chip comprising an electrical contact buried into the bonding layer; and
a buildup layer on a second major surface of the bonding layer opposite the first major surface and substantially surrounding the distribution circuitry.

7. The semiconductor device of claim 6 , further comprising solder bumps coupled to the distribution circuitry, wherein the buildup layer secures, in part, the solder bumps.

8. The semiconductor device of claim 6 , wherein the adhesive layer is configured to release the carrier layer with respect to the bonding layer upon the adhesive layer being debonded.

9. The semiconductor device of claim 6 , wherein the debondable adhesive layer comprises one of a thermo-releasable adhesive and an ultra-violet-releasable adhesive configured to be debonded upon application of at least one of heat and ultra-violet energy.

10. The semiconductor device of claim 6 , wherein the chip comprises a plurality of electrical contacts each having approximately two (2) micrometers of separation between one another.

11. The semiconductor device of claim 6 , wherein the bonding layer is a polyamide epoxy.

Assignees

• Hu Chuan
• Intel Corp

Inventors

• Hu Chuan

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title