Wafer level shielding in multi-stacked fan out packages and methods of forming same

Patent metadata

Field	Value
Publication number	US-9659878-B2
Application number	US-201514918311-A
Country	US
Kind code	B2
Filing date	Oct 20, 2015
Priority date	Oct 20, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.

First claim

What is claimed is:

1. A method for forming a device package comprising:
forming first conductive through inter-vias (TIVs) over a carrier substrate;
attaching a first device die to the carrier substrate, wherein the first device die is disposed between adjacent ones of the first conductive TIVs;
forming a first molding compound around the first device die and the first conductive TIVs;
exposing the first conductive TIVs; and
forming an electromagnetic interference (EMI) shield over the first device die and extending along sidewalls of the first molding compound, wherein the EMI shield contacts the first conductive TIVs, and wherein the first conductive TIVs electrically connect the EMI shield to external connectors formed on an opposing side of the first device die as the EMI shield.

2. The method of claim 1 , wherein forming the first conductive TIVs comprises forming the first conductive TIVs over a polymer layer disposed over the carrier substrate, wherein exposing the first conductive TIVs comprises laser etching openings in the polymer layer, and wherein forming the EMI shield comprises forming the EMI shield at least partially in the openings in the polymer layer.

3. The method of claim 1 , wherein forming the first conductive TIVs comprises forming the first conductive TIVs over a polymer layer disposed over the carrier substrate, wherein exposing the first conductive TIVs comprises removing the polymer layer.

4. The method of claim 1 further comprising patterning openings in a polymer layer disposed over the carrier substrate, wherein forming the first conductive TIVs comprises forming the first conductive TIVs extending through the openings in the polymer layer, and wherein exposing the first conductive TIVs comprises removing the carrier substrate.

5. The method of claim 1 further comprising:
forming fan-out redistribution layers (RDLs) over the first molding compound, the first device die, and the first conductive TIVs;
forming the external connector over the fan-out RDLs; and
prior to exposing the first conductive TIVs, flipping an orientation of the device package.

6. The method of claim 5 further comprising:
forming second conductive TIVs over the fan-out RDLs;
disposing a second device die over the fan-out RDLs, wherein the second device die is disposed between adjacent ones of the second conductive TIVs;
forming a second molding compound around the second device die and the second conductive TIVs; and
forming additional fan-out RDLs over the second molding compound, the second device die, and the second conductive TIVs, wherein the additional fan-out RDLs, the second TIVs, and the fan-out RDLs electrically connect the EMI shield to the external connector.

7. The method of claim 1 further comprising electrically connecting the external connector to ground.

8. The method of claim 1 further comprising:
prior to forming the EMI shield, patterning an opening extending partially through a package wafer comprising the device package, wherein forming the EMI shield comprises forming a portion of the EMI shield in the opening; and
after forming the EMI shield, singulating the device package from the package wafer.

9. The method of claim 8 further comprising disposing a scatter shield at edges of the package wafer while forming the EMI shield.

10. A method comprising:
depositing a polymer layer over a carrier;
forming a first conductive via over the polymer layer;
disposing a semiconductor die adjacent the first conductive via and over the polymer layer;
encapsulating the semiconductor die and the first conductive via in a molding compound;
forming redistribution layers (RDLs) over the first conductive via and the semiconductor die;
removing the carrier;
after removing the carrier, exposing the first conductive via;
forming an electromagnetic interference (EMI) shield on an opposing side of the semiconductor die as the RDLs and extending along sidewalls of the molding compound, wherein the EMI shield contacts the first conductive via.

11. The method of claim 10 further comprising forming an external connector on an opposing side of the RDLs as the semiconductor die, wherein the RDLs electrically connect the EMI shield to the external connector.

12. The method of claim 10 , wherein exposing the first conductive via comprises removing the polymer layer.

13. The method of claim 10 , wherein exposing the first conductive via comprises laser etching an opening through the polymer layer to expose the first conductive via.

14. The method of claim 13 , wherein forming the EMI shield comprises forming a portion of the EMI shield in the opening.

15. The method of claim 13 , wherein the EMI shield further extends along sidewalls of the RDLS.

16. A method comprising:
patterning an opening through a polymer layer;
forming a first conductive via over the polymer layer and extending through the opening in the polymer layer;
disposing a first die adjacent the first conductive via over the polymer layer;
encapsulating the first die and the first conductive via with a first molding compound;
forming first redistribution layers (RDLs) electrically connected to the first conductive via and the first die; and
forming an electromagnetic interference (EMI) shield on an opposing side of the first die as the first RDLs, wherein a portion the polymer layer is disposed between the EMI shield and the first die, and wherein the EMI shield contacts the first conductive via.

17. The method of claim 16 wherein forming the first conductive via comprises:
depositing a seed layer over the polymer layer and along sidewalls of the opening in the polymer layer; and
plating the first conductive via on the seed layer.

18. The method of claim 16 , wherein the polymer layer is disposed over a carrier, and wherein the method further comprises removing the carrier to expose the first conductive via.

19. The method of claim 16 further comprising:
disposing a second die on an opposing side of the first RDLs as the first die;
encapsulating the second die in a second molding compound;
forming second redistribution layers (RDLs) electrically connected to the second die on an opposing side of the second dies as the first RDLs; and
forming an external connector on an opposing side of the second RDLs as the second die, wherein the external connector is electrically connected to the EMI shield through the first conductive via.

20. The method of claim 19 , wherein a line extending along a bottom surface of the EMI shield also extends through the second die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Yu
• Chen Hsien-Wei
• Su An-Jhih
• Wang Jo-Mei
• Yang Tien-Chung

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title