Semiconductor die substrate with integral heat sink

Patent metadata

Field	Value
Publication number	US-9659844-B2
Application number	US-201514841081-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

An integrated circuit device includes a semiconductor substrate with a top surface, a bottom surface opposite the top surface and an intermediate portion positioned between the top and bottom surfaces. The device also includes interior substrate surfaces defined by at least one void extending from the bottom surface to the intermediate portion.

First claim

What is claimed is:

1. An integrated circuit package comprising:
an integrated circuit device including a semiconductor substrate with a top surface, a bottom surface opposite said top surface, opposite first and second lateral side surfaces and opposite first and second longitudinal end surfaces, an intermediate portion positioned between said top and bottom surfaces and dividing said semiconductor substrate into upper and lower substrate portions, and interior surfaces defined by at least one void extending from said bottom surface to said intermediate portion and thermally conductive material interfacing with said interior surfaces; and
an encapsulant encapsulating at least a portion of said substrate and a portion of said leadframe, wherein at least part of said lower substrate portion extends outwardly of said encapsulant.

2. The integrated circuit package of claim 1 , further comprising thermally conductive material interfacing with said interior surfaces.

3. The integrated circuit package of claim 2 wherein said thermally conductive material comprises at least one of metal, graphite, grapheme, diamond, zinc oxide, indium phosphide, thermal epoxy and thermally conductive oxide.

4. The integrated circuit package of claim 2 wherein said thermally conductive material interfacing with said interior surfaces comprises a surface coating layer.

5. The integrated circuit package of claim 2 wherein said thermally conductive material interfacing with said interior surfaces at least partially fills said at least one void.

6. The integrated circuit package of claim 5 wherein said thermally conductive material completely fills said at least one void.

7. An integrated circuit device including a semiconductor substrate with a top surface, a bottom surface opposite said top surface, opposite first and second lateral side surfaces and opposite first and second longitudinal end surfaces, an intermediate portion positioned between said top and bottom surfaces and dividing said semiconductor substrate into upper and lower substrate portions, and interior surfaces defined by at least one void extending from said bottom surface to said intermediate portion and thermally conductive material interfacing with said interior surfaces; and
wherein said thermally conductive material extends outwardly of at least one of said opposite first and second lateral side surfaces and opposite first and second longitudinal end surfaces of said substrate.

8. The device of claim 2 wherein said thermally conductive material is also an electrically conductive material.

9. The device of claim 2 wherein said thermally conductive material is an electrically nonconductive material.

10. The device of claim 1 wherein said at least one void is filled with fluid.

11. The device of claim 10 wherein said fluid filling said at least one void is moving within said at least one void.

12. The device of claim 10 wherein said fluid is air.

13. The device of claim 10 wherein said fluid is a liquid coolant.

14. The device of claim 2 further comprising a leadframe bonded to said thermally conductive material.

15. The device of claim 1 , said device comprising a flip chip having solder balls attached to said top surface of said substrate.

16. An integrated circuit device comprising:
a first semiconductor substrate with a top surface, a bottom surface opposite said top surface, an intermediate portion positioned between said top and bottom surfaces and interior surfaces defined by at least one void extending from said bottom surface to said intermediate portion;
thermally conductive material interfacing with said interior surfaces of said first semiconductor substrate;
a second substrate having a top surface and a bottom surface that is positioned in stacked relationship with said first substrate; and
at least one filled via extending from said top surface to said bottom surface of said second substrate.

17. The device of claim 16 further comprising a leadframe on which one of said first and second substrates is mounted.

18. The device of claim 1 wherein said at least one void comprises a plurality of longitudinally extending channels and a plurality of laterally extending channels that intersect said plurality of longitudinally extending channels.

19. The device of claim 18 wherein said longitudinally extending channels extend through opposite lateral sidewalls of said semiconductor substrate.

20. The device of claim 2 wherein said thermally conductive material has a coefficient of thermal expansion (“CTE”) approximately the same as that of the semiconductor material of the substrate.

21. The device of claim 20 wherein the CTE of the thermally conductive material differs from the CTE of the semiconductor material by less than 15%.

22. An integrated circuit package comprising:
a lead frame comprising a die pad and a plurality of leads;
a first semiconductor die substrate attached at a bottom surface thereof to said die pad, said first substrate having a plurality of laterally extending slots with openings of said slot located at said bottom surface of said first substrate;
a first clip member attached at one end to a metal circuit layer on the top of said first die and on the other end to at least one of said plurality of leads;
a second semiconductor die substrate attached at a bottom surface thereof to said first clip member, said second substrate having a plurality of slots extending laterally therethrough with openings of said slots located at said bottom surface of said second substrate, thermally conductive material at least partially filling said plurality of slots in said first die and said plurality of slots in said second die; and
a second clip member attached at one end to a metal circuit layer on the top of said second die and on the other end to at least one of said plurality of leads and wherein said thermally conductive material has a coefficient of thermal expansion near that of said semiconductor material in the corresponding die.

23. The integrated circuit package of claim 22 wherein said thermally conductive material comprises at least two different thermally conductive materials.

24. The integrated circuit package of claim 22 wherein said first and second dies comprise first and second FETs, respectively.

Assignees

• Texas Instruments Inc

Inventors

• Mukhopadhyay Rajarshi
• Carothers Daniel N
• Cook Benjamin

Classifications

• H10W72/07651

  characterised by changes in properties of the strap connectors during connecting · CPC title

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/421

  Shapes or dispositions · CPC title