Programmable logic applications for an array of high on/off ratio and high speed non-volatile memory cells

Patent metadata

Field	Value
Publication number	US-9659646-B1
Application number	US-201614992718-A
Country	US
Kind code	B1
Filing date	Jan 11, 2016
Priority date	Jan 11, 2016
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

First claim

What is claimed is:

1. A network router device, comprising:
a plurality of programmable logic devices each comprising a transistor of a set of transistors, respective transistors having a gate, a source and a drain, and comprising a resistive memory device of a set of resistive memory devices, respective resistive memory devices having a first terminal and a second terminal, wherein respective drains of the set of transistors are coupled to respective first terminals of the set of resistive memory devices for each of the plurality of programmable logic devices, and respective second terminals of the set of resistive memory devices are coupled to a ground, and wherein each of the set of resistive memory devices is characterized by programmable high resistance or low resistance state;
a plurality of logical inputs, wherein each of the plurality of logical inputs is coupled to the gate of respective transistors of the set of transistors; and
a logical output coupled to the sources of the respective transistors;
wherein the set of resistive memory devices is configured to have a programmable pattern of resistance states, the programmable pattern comprising a high resistance state, a low resistance state, or a combination of high resistance and low resistance states.

2. The device of claim 1 ,
wherein a logical input from the plurality of logical inputs is coupled to a programmable logic device from the plurality of programmable logic devices;
wherein when the logical input has a high signal, the logical output is electrically coupled to the first terminal of a resistive memory device of the set of resistive memory devices associated with the programmable logic device; and
wherein when the logical input has a low signal, a the logical output is electrically decoupled from the first terminal of the one of the set of resistive memory devices.

3. The device of claim 2 ,
wherein when the logical input is high and the resistive memory device is in the low resistance state, the logical output is coupled to ground through a low resistance; and
wherein when the logical input is high and the resistive memory device is in the high resistance state, the logical output is coupled to ground through a high resistance.

4. The device of claim 3 , further comprising a pull-up circuit coupled to the logical output, wherein the pull-up circuit is configured to provide a supply voltage to the logical output.

5. The device of claim 4 ,
wherein when the logical input is high and the resistive memory device is in the low resistance state, the logical output is reduced below the supply voltage; and
wherein when the logical input is high and the resistive memory device is in the high resistance state, the logical output remains at substantially the supply voltage.

6. The device of claim 4 ,
wherein when the logical input is low, the resistive memory device is electrically decoupled from the logical output, and the logical output remains at substantially the supply voltage.

7. The device of claim 1 ,
wherein the plurality of programmable logic devices comprises a first programmable logic device having a first resistive memory device and a second programmable logic device having a second resistive memory device;
wherein the programmable pattern of resistance states comprises a high resistance state stored at the first resistive memory device and a low resistance state stored at the second resistive memory device;
wherein the plurality of logical inputs comprises a first logical input coupled to the first programmable logic device and a second logical input coupled to the second programmable logic device;
wherein the logical output is low in response to the second logical input being high; and
wherein the logical output is high in response to the second logical input being low.

8. The device of claim 1 , further comprising:
a plurality of switching devices each comprising a transistor of a second set of transistors having a gate, a source and a drain, and comprising a memory device of a set of memory devices having a first terminal and a second terminal, wherein each drain of the second set of transistors is coupled to respective first terminals of the set of memory devices, and the second terminals of the set of memory devices are coupled to ground;
a plurality of output lines respectively coupled to one source of the second set of transistors;
wherein the logical output is coupled to each gate of the second set of transistors.

9. The device of claim 8 ,
wherein when the logical output is high, the second set of transistors is activated and respective output lines of the plurality of output lines are coupled to respective first terminals of the set of memory devices; and
wherein when the logical output is low, the set of transistors are deactivated and the respective output lines of the plurality of output lines are decoupled from the respective first terminals of the set of memory devices.

10. The device of claim 8 ,
wherein when the logical output is high and a memory device of the set of memory devices is in the low resistance state, an output line of the plurality of output lines associated with the memory device is pulled low; and
wherein when the logical output is high and the memory device of the set of memory devices is in the high resistance state, the output line of the plurality of output lines associated with the memory device is high.

11. An apparatus comprising a circuit, the circuit comprising:
a set of input lines configured to receive an input;
an output line;
a pullup-circuit connected to and configured to apply a default voltage to the output line;
a set of programmable two-terminal switching devices respectively having a first terminal and a second terminal, wherein respective first terminals of the set of programmable two-terminal switching devices are coupled to respective ones of the set of input lines and the second terminals of the set of programmable two-terminal switching devices are coupled to the output line, wherein:
the set of programmable two-terminal switching devices are programmed to a programmed pattern,
the set of programmable two-terminal switching devices are in a non-conductive state in response to the input matching the programmed pattern; and
at least one of the set of programmable two-terminal switching devices is in a conductive state in response to the input not matching the programmed pattern.

12. The apparatus of claim 11 , wherein the default voltage on the output line changes in magnitude in response to the at least one of the set of programmable two-terminal switching devices being in the conductive state.

13. The apparatus of claim 12 , wherein the default voltage on the output line validates a logical AND of the input signal and the programmed pattern.

14. The apparatus of claim 12 , wherein the changed magnitude of the default voltage on the output line invalidates a logical AND of the input signal and the programmed pattern.

15. The apparatus of claim 11 , further comprising:
a second output line;
a second pullup-circuit connected to and configured to apply the default voltage to the second output line;
a second set of programmable two-terminal switching devices, each programmable two-terminal switching device of the second set of programmable two-terminal switching devices having a first terminal and a second terminal, wherein respective first terminals of the second set of programmable two-terminal switching devices are coupled to the respective input lines and respective second terminals of the second set of programmable two-terminal switching de

Assignees

• Crossbar Inc

Inventors

• Asnaashari Mehdi
• Nazarian Hagop
• Liu Lin Shih

Classifications

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• H04L49/9063

  Intermediate storage in different physical parts of a node or terminal · CPC title

• G11C15/046

  using non-volatile storage elements · CPC title