Achieving power saving by a circuit including pluralities of processing cores based on status of the buffers used by the processing cores

Patent metadata

Field	Value
Publication number	US-9658675-B1
Application number	US-201514626637-A
Country	US
Kind code	B1
Filing date	Feb 19, 2015
Priority date	Feb 19, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Subject matter disclosed herein relates to arrangements and techniques that provide for sending messages among processing nodes over a network-on-chip (NoC). More particularly, the present disclosure provides an Application Specific Integrated Circuit (ASIC) that includes processing cores and co-processors. The processing cores and co-processors are coupled together with a NoC. Each processing core and co-processor includes two corresponding buffers. A first buffer is for sending messages and a second buffer is for receiving messages. If a processing core or co-processor needs to send a message and the corresponding first buffer is full, if the message includes a flag that indicates a WAIT function, then the processing core and/or co-processor enters a low power state until the first buffer is available; otherwise the message is ignored and not sent. Additionally, if a second buffer is empty, then the corresponding processing core and/or co-processor enters the low power state.

First claim

What is claimed is:

1. An Application Specific Integrated Circuit (ASIC) including:
a first processing core, wherein the first processing core includes a first send first-in first-out (FIFO) buffer and a first receive FIFO buffer;
a second processing core, wherein the second processing core includes a second send FIFO buffer and a second receive FIFO buffer;
a third processing core, wherein the third processing core includes a third send FIFO buffer and a third receive FIFO buffer;
a fourth processing core, wherein the fourth processing core includes a fourth send FIFO buffer and a fourth receive FIFO buffer;
memory; and
a network-on-chip (NoC) coupled to the first, second, third and fourth processing cores and the memory, wherein the processing cores are configured to (i) send messages to other processing cores via the NoC, (ii) receive messages from the other processing cores via the NoC, (iii) write data to the memory via the NoC and (iv) read data from the memory via the NoC;
wherein at least the first processing core is configured such that when a message that includes a WAIT function is to be sent by the first processing core to one of (i) the second processing core or (ii) the memory and the send FIFO buffer of the first processing core is full, the first processing core enters a low power state until the send FIFO buffer of the first processing core is not full, and
wherein at least the first processing core is further configured such that if the first receive FIFO buffer of the first processing core is empty, the first processing core enters the low power state.

2. The ASIC of claim 1 , wherein entering the low power state comprises deactivating a first clock of the first processing core, wherein the first clock comprises one or more of a clock for instruction fetching, a clock for instruction decoding, a clock for instruction execution, a clock for memory writing-back, and a clock for register writing-back.

3. The ASIC of claim 2 , wherein a second clock of the first processing core is not deactivated, the second clock being used to one or more of (i) send and receive messages, (ii) handle traffic to and from the memory of the corresponding processing core, or (iii) handle interrupts.

4. The ASIC of claim 1 , wherein at least the first processing core is further configured to ignore a message if the first send FIFO buffer is full and the message does not include a WAIT function.

5. The ASIC of claim 1 , wherein at least the first processing core is further configured such that if a controller of the NoC indicates that the second receive FIFO buffer of the second processing core is full, the first processing core enters the low power state.

6. The ASIC of claim 1 , further comprising:
a first co-processor associated with the first processing core and coupled to the NoC, wherein the first co-processor includes a send FIFO buffer and a receive FIFO buffer;
a second co-processor associated with the second processing core and coupled to the NoC, wherein the second co-processor includes a send FIFO buffer and a receive FIFO buffer;
a third co-processor associated with the third processing core and coupled to the NoC, wherein the third processing core includes a send FIFO buffer and a receive FIFO buffer; and
a fourth co-processor associated with the fourth processing core and coupled to the NoC, wherein the fourth processing core includes a send FIFO buffer and a receive FIFO buffer,
wherein the co-processors are configured to (i) send messages to other co-processors via the NoC, (ii) receive messages from the other co-processors via the NoC, (iii) write data to the memory via the NoC and (iv) read data from the memory via the NoC,
wherein at least the first co-processor is configured such that when a message that includes a WAIT function is to be sent by the first co-processor to one of (i) the second co-processor or (ii) the memory and the send FIFO buffer of the first co-processor is full, the first co-processor enters a low power state until the send FIFO buffer of the first co-processor is not full, and
wherein at least the first co-processor is further configured such that if the first receive FIFO buffer of the first co-processor is empty, the first co-processor enters the low power state.

7. A circuit including:
a plurality of processing cores, wherein each processing core includes a corresponding first FIFO buffer and a corresponding second FIFO buffer; and
a network-on-chip (NoC) coupled to the plurality of processing cores;
wherein the plurality of processing cores is configured to send and receive messages via the NoC, and wherein at least a first processing core is configured such that when a message that includes a flag that indicates a WAIT function is to be sent by the first processing core to one of (i) a second processing core of the plurality of processing cores or (ii) memory and the first FIFO buffer of the first processing core is full, the first processing core enters a low power state.

8. The circuit of claim 7 , wherein the at least the first processing core is further configured to ignore a message if the first FIFO buffer is full and the message does not include a flag that indicates a WAIT function.

9. The circuit of claim 7 , wherein at least the first processing core is further configured such that when the first processing core enters the low power state, the first processing core remains in the low power state until the first buffer of the first processing core is no longer full.

10. The circuit of claim 9 , wherein entering the low power state comprises deactivating a first clock of the first processing core, wherein the first clock comprises one or more of a clock for instruction fetching, a clock for instruction decoding, a clock for instruction execution, a clock for memory writing-back, and a clock for register writing-back.

11. The circuit of claim 10 , wherein a second clock that is not deactivated is used to one or more of (i) send and receive messages, (ii) handle traffic to and from memory, and (iii) handle interrupts.

12. The circuit of claim 7 , wherein at least the first processing core is further configured such that if a controller of the NoC indicates that the second receive FIFO buffer of the second processing core is full, the first processing core enters the low power state.

13. The circuit of claim 7 , wherein the second FIFO buffer is for receiving messages from other processing cores, and wherein at least the first processing core is further configured such that if the second buffer of the first processing core is empty, the first processing core enters the low power state.

14. The circuit of claim 7 , further comprising:
a plurality of co-processors, wherein each co-processor includes a corresponding first FIFO buffer and a corresponding second FIFO buffer, and wherein each co-processor is associated with a corresponding processing core;
wherein the plurality of co-processors is configured to send and receive messages via the NoC, and wherein at least a first co-processor of the plurality of co-processors is configured such that when a message that includes a flag that indicates a WAIT function is to be sent by the first co-processor to one of (i) a second co-processor of the plurality of co-processors or (ii) memory and the first FIFO buffer of the first co-processor is full, the first co-processor enters a low power state.

15. The circuit of claim 14 , wherein at least the first co-processor is further configured to ignore a message if the first FIFO buffer is full and the message does not include a flag that indicates a WAIT function.

Assignees

• Amazon Tech Inc

Inventors

• Witek Richard Thomas
• Li Long
• Suresh Maya

Classifications

• G06F1/3237 Primary

  by disabling clock generation or distribution · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F15/173

  using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake · CPC title