Low latency data exchange between processing elements
US-2016364352-A1 · Dec 15, 2016 · US
Message broadcast with router bypassing
US9015448B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9015448-B2 |
| Application number | US-81794510-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 17, 2010 |
| Priority date | Jun 17, 2010 |
| Publication date | Apr 21, 2015 |
| Grant date | Apr 21, 2015 |
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Abstract
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A processor and method for broadcasting data among a plurality of processing cores is disclosed. The processor includes a plurality of processing cores connected by point-to-point connections. A first of the processing cores includes a router that includes at least an allocation unit and an output port. The allocation unit is configured to determine that respective input buffers on at least two others of the processing cores are available to receive given data. The output port is usable by the router to send the given data across one of the point-to-point connections. The router is configured to send the given data contingent on determining that the respective input buffers are available. Furthermore, the processor is configured to deliver the data to the at least two other processing cores in response to the first processing core sending the data once across the point-to-point connection.
First claim
Opening claim text (preview).
What is claimed: 1. An apparatus, comprising: a plurality of processing cores connected by a plurality of point-to-point connections within the apparatus, wherein: the plurality of processing cores includes at least a first processing core, a second processing core, and a third processing core, wherein the first processing core is configured to send a set of data across one of the plurality of point-to-point connections in response to determining that both the first and the seco…
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- G06F15/17337Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9015448B2 cover?
- A processor and method for broadcasting data among a plurality of processing cores is disclosed. The processor includes a plurality of processing cores connected by point-to-point connections. A first of the processing cores includes a router that includes at least an allocation unit and an output port. The allocation unit is configured to determine that respective input buffers on at least two…
- Who is the assignee on this patent?
- Krishna Tushar, Beckmann Bradford M, Reinhardt Steven K, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F15/17337. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).