Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in RRAM devices

Patent metadata

Field	Value
Publication number	US-9653680-B2
Application number	US-201514752934-A
Country	US
Kind code	B2
Filing date	Jun 27, 2015
Priority date	Jun 27, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer.

First claim

The invention claimed is:

1. A method for forming a resistive random access memory device, comprising:
forming a first electrode over a substrate;
forming a dielectric region on lateral portions of the first electrode;
forming a resistive random access memory oxide layer over the first electrode and the dielectric regions;
forming a recess region in the resistive random access memory oxide layer;
forming a second electrode over the resistive random access memory oxide layer wherein a portion of the second electrode fills the recess region;
patterning the second electrode and the resistive random access memory oxide layer to expose the dielectric region on the lateral portions of the first electrode; and
extending the dielectric region on the lateral portions of the first electrode to cover lateral portions of the resistive random access memory oxide layer and the second electrode.

2. The method of claim 1 , wherein forming the recess region includes forming a first recess having a first area and forming a second recess having a second area wherein the first area is less than the second area.

3. The method of claim 2 , wherein forming the recess region includes:
forming a hardmask layer on the resistive random access memory oxide layer;
forming an opening in the hardmask layer;
forming a spacer material within the opening; and
etching the recess region into the top center portion of resistive random access memory oxide layer;
wherein etching the recess region forms the first recess.

4. The method of claim 3 further comprising etching a second recess within the recess region.

5. The method of claim 1 further comprising forming an oxygen exchange layer on the first electrode wherein the oxygen exchange layer is disposed between the first electrode and the resistive random access memory oxide layer.

6. The method of claim 1 further comprising forming a metal layer on the first electrode; wherein the metal layer is disposed between the first electrode and the resistive random access memory oxide.

Assignees

• Intel Corp

Inventors

• Pillarisetty Ravi
• Majhi Prashant
• Shah Uday
• Mukherjee Niloy
• Karpov Elijah V
• Doyle Brian S
• Chau Robert S

Classifications

• H01L45/1253

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/1675

  Electricity · mapped topic

• H01L45/122 Primary

  Electricity · mapped topic

• H10N70/8418

  adapted for focusing electric field or current, e.g. tip-shaped · CPC title