Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device

US9653538B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9653538-B2
Application numberUS-201414220542-A
CountryUS
Kind codeB2
Filing dateMar 20, 2014
Priority dateMar 21, 2013
Publication dateMay 16, 2017
Grant dateMay 16, 2017

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  5. First independent claim

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Abstract

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A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

First claim

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What is claimed is: 1. A method of localized stress modification in a substrate of the initially tensile-stressed silicon on insulator type, said substrate comprising an initially tensile-stressed semi-conducting silicon film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate, the method comprising: forming at least one opening in the initially tensile-stressed semi-conducting silicon film and in the underlying buried insulating layer until the unstressed silicon support substrate is reached, performing a silicon epitaxy in the at least one opening from the unstressed silicon support substrate so as to fill in the at least one opening, performing a localized amorphization of a zone of the initially tensile-stressed semi-conducting silicon film including the silicon epitaxy in the at least one opening, and recrystallizing the localized amorphized zone by a solid-phase epitaxy from the unstressed silicon support substrate situated in the at least one opening so as to obtain at least one localized film zone comprising tensile-relaxed silicon. 2. The method according to claim 1 , wherein the substrate is of fully depleted initially tensile-stressed silicon on insulator type. 3. The method according to claim 1 , wherein the opening is formed at the level of a well for allowing a contact with the unstressed silicon support substrate from the upper face of the initially tensile-stressed semi-conducting silicon film. 4. The method according to claim 1 , further comprising forming a germanium silicon alloy in at least one part of the localized film zone comprising tensile-relaxed silicon, so as to form a compressive-stressed film zone. 5. A method for producing transistors of the N channel type and transistors of the P channel type in a substrate of initially stressed silicon on insulator type, said substrate comprising an initially tensile-stressed semi-conducting silicon film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate, the method comprising: forming at least one opening in the initially tensile-stressed semi-conducting silicon film and in the underlying buried insulating layer, said at least one opening extending to reach the unstressed silicon support substrate, performing a silicon epitaxy in the at least one opening from the unstressed silicon support substrate so as to fill in the at least one opening, performing a localized amorphization of a zone of the initially tensile-stressed semi-conducting silicon film including the silicon epitaxy in the at least one opening, recrystallizing the localized amorphized zone by a solid-phase epitaxy from the unstressed silicon support substrate situated in the at least one opening so as to obtain at least one localized film zone comprising tensile-relaxed silicon, producing a P channel transistor in the localized film zone comprising tensile-relaxed silicon, and producing an N channel transistor in a region of the initially tensile-stressed semi-conducting silicon film. 6. A method for producing transistors of the N channel type and transistors of the P channel type in a substrate of initially stressed silicon on insulator type, said substrate comprising an initially tensile-stressed semi-conducting silicon film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate, the method comprising: forming at least one opening in the initially tensile-stressed semi-conducting silicon film and in the underlying buried insulating layer, said at least one opening extending to reach the unstressed silicon support substrate, performing a silicon epitaxy in the at least one opening from the unstressed silicon support substrate so as to fill in the at least one opening, performing a localized amorphization of a zone of the initially tensile-stressed semi-conducting silicon film including the silicon epitaxy in the at least one opening, recrystallizing the localized amorphized zone by a solid-phase epitaxy from the unstressed silicon support substrate situated in the at least one opening so as to obtain at least one localized film zone comprising tensile-relaxed silicon, forming a germanium silicon alloy in at least one part of the localized film zone comprising tensile-relaxed silicon so as to form a compressive-stressed film zone, producing a P channel transistor in the compressive-stressed film zone, and producing an N channel transistor in a region of the initially tensile-stressed semi-conducting silicon film. 7. A method, comprising: forming an opening in a silicon on insulator substrate, said substrate comprising an initially tensile-stressed semi-conducting silicon film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate, said opening extending completely through both the initially tensile-stressed semi-conducting silicon film and the buried insulating layer; epitaxially growing silicon material to fill said opening; locally amorphizing a region including a portion of the epitaxially grown silicon material and a portion of the initially tensile-stressed semi-conducting silicon film; recrystallizing the locally amorphized region by a solid-phase epitaxy so as to obtain a tensile-relaxed silicon region adjacent a tensile-stressed region formed from the initially tensile-stressed semi-conducting silicon film. 8. The method of claim 7 , further comprising: forming an N channel transistor in the tensile-stressed region; and forming a P channel transistor in the tensile-relaxed silicon region. 9. The method of claim 7 , further comprising: epitaxially growing silicon-germanium material on the tensile-relaxed silicon region. 10. The method of claim 9 , further comprising performing a condensation to drive germanium from the silicon-germanium material into the tensile-relaxed silicon region to form a compressive-stressed region. 11. The method of claim 10 , further comprising: forming an N channel transistor in the tensile-stressed region; and forming a P channel transistor in the compressive-stressed region.

Assignees

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Classifications

  • Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • being non-crystalline insulating materials, e.g. glass or polymers · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • characterised by the preparation of substrate for selective deposition · CPC title

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What does patent US9653538B2 cover?
A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon supp…
Who is the assignee on this patent?
St Microelectronics Crolles 2 Sas, Commissariat Energie Atomique
What technology area does this patent fall under?
Primary CPC classification H10P14/3802. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 16 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).