Multi-layer interconnected spiral capacitor

Patent metadata

Field	Value
Publication number	US-9653533-B2
Application number	US-201514625484-A
Country	US
Kind code	B2
Filing date	Feb 18, 2015
Priority date	Feb 18, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

First claim

What is claimed is:

1. A multi-layer capacitor, comprising:
a first level planar capacitor, comprising a first level first trace and a first level second trace;
a dielectric layer, arranged over the first level planar capacitor;
a second level planar capacitor, arranged over the dielectric layer, comprising a second level first trace and a second level second trace; and
a bridged-post inter-layer interconnect, comprising
at least two first posts and at least two second posts, extending through the dielectric layer, adjacent to and outside a perimeter of the first level planar capacitor and a perimeter of the second level planar capacitor,
a first level first post coupler and a first level second post coupler, under the dielectric layer, wherein the first level first post coupler is configured to couple the at least two first posts together and to the first level first trace, and the first level second post coupler is configured to couple the first level second trace to at least one of the at least two second posts, and
a second level first post coupler and a second level second post coupler, over the dielectric layer, wherein the second level second post coupler is configured to couple the at least two second posts together and to the second level first trace, and the second level first post coupler is configured to couple the second level first trace to at least one of the at least two first posts.

2. The multi-layer capacitor of claim 1 , wherein the first level first trace and the first level second trace are configured to extend adjacent each other, along mutually parallel paths, wherein the mutually parallel paths are in a plane.

3. The multi-layer capacitor of claim 2 , wherein the second level first trace is configured in a tracking alignment above the first level first trace, to form a first parallel plate capacitor, and wherein the second level second trace is configured in a tracking alignment above the first level second trace, to form a second parallel plate capacitor.

4. The multi-layer capacitor of claim 1 , wherein the first level planar capacitor is a first level spiral capacitor, and the second level planar capacitor is a second level spiral capacitor,
wherein the first level first trace comprises a first level first spiral winding, the first level second trace comprises a first level second spiral winding, wherein the first level second spiral winding and the first level first spiral winding are interwound around a winding axis,
wherein the second level first trace comprises a second level first spiral winding, the second level second trace comprises a second level second spiral winding, wherein second level second spiral winding and the second level first spiral winding are interwound around the winding axis, wherein the second level first spiral winding is configured in a tracking alignment with the first level first spiral winding, and the second level second spiral winding is configured in a tracking alignment with the first level second spiral winding.

5. The multi-layer capacitor of claim 4 , wherein the first level first spiral winding is a first level first rectangular spiral winding, the first level second spiral winding is a first level second rectangular spiral winding, the second level first spiral winding is a second level first rectangular spiral winding, and the second level second spiral winding is a second level second rectangular spiral winding.

6. The multi-layer capacitor of claim 4 , wherein the dielectric layer is a first dielectric layer, wherein the multi-layer capacitor further comprises:
a third level spiral capacitor, spaced above the second level spiral capacitor by a second dielectric layer, comprising a third level first spiral winding and a third level second spiral winding, wherein the third level first spiral winding and the third level second spiral winding are interwound around the winding axis, wherein the third level first spiral winding is in a tracking alignment above the second level first spiral winding to form a third parallel plate capacitor, and wherein the third level second spiral winding is configured in a tracking alignment above the second level second spiral winding to form a fourth parallel plate capacitor; and
a fourth level spiral capacitor, spaced above the third level spiral capacitor by a third dielectric layer, comprising a fourth level first spiral winding and a fourth level second spiral winding, wherein the fourth level first spiral winding and the fourth level second spiral winding are interwound around the winding axis, wherein the fourth level first spiral winding is in a tracking alignment with the third level first spiral winding to form a fifth parallel plate capacitor, and wherein the fourth level second spiral winding is configured in a tracking alignment with the third level second spiral winding to form a sixth parallel plate capacitor.

7. The multi-layer capacitor of claim 6 , wherein the at least two first posts and the at least two second posts are configured to further extend, normal to the plane, through the second dielectric layer and through the third dielectric layer, and wherein the bridged-post inter-layer interconnect further comprises:
a third level first post coupler, above the second dielectric layer, configured to couple the at least two first posts together and to the third level first spiral winding,
a third level second post coupler, configured to couple the third level second spiral winding to at least one of the at least two second posts;
a fourth level second post coupler, above the third dielectric layer, configured to couple the at least two second posts together and to the fourth level first spiral winding; and
a fourth level first post coupler, configured to couple the fourth level second spiral winding to at least one of the at least two first posts.

8. The multi-layer capacitor of claim 1 , wherein the dielectric layer is a first dielectric layer, and wherein the multi-layer capacitor further comprises a third level planar capacitor, spaced above the second level planar capacitor by a second dielectric layer, wherein the second level planar capacitor comprises a third level first trace and a third level second trace, configured adjacent each other and parallel to the plane,
wherein the third level first trace is configured in a tracking alignment above the second level first trace to form a third parallel plate capacitor, and
wherein the third level second trace is configured in a tracking alignment above the second level second trace to form a fourth parallel plate capacitor.

9. The multi-layer capacitor of claim 8 , wherein the at least two first posts and the at least two second posts are additionally configured to further extend, normal to the plane, through the second dielectric layer, and wherein the bridged-post inter-layer interconnect further comprises:
a third level first post coupler, above the second dielectric layer, configured to couple the at least two first posts together and to the third level first trace; and
a third level second post coupler, above the second dielectric layer, configured to couple the third level second trace to at least one of the at least two second posts.

10. The multi-layer capacitor of claim 1 , wherein the first level first trace includes a first level first trace start, and the first level second trace includes a first level second trace start, wherein the first level second trace start is proximal to the first level first trace start, and
wherein the second level first trace includes a second level first trace start, wherein the second level first trace start is laterally aligned above the first level first trace start, and the second level second t

Assignees

• Qualcomm Inc

Inventors

• Jow Uei-Ming
• Song Young Kyu
• Lee Jong-Hoon
• Zhang Xiaonan

Classifications

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H01L28/60

  Electricity · mapped topic

• H01G4/33

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H01L23/5223

  Electricity · mapped topic