Multi-chip structure and method of forming same

Patent metadata

Field	Value
Publication number	US-9653433-B2
Application number	US-201615085837-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Aug 13, 2013
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer, and wherein at least one edge of the first chip and the second chip is exposed outside the encapsulation layer, a redistribution layer on a surface of a first side of the encapsulation layer and a plurality of conductive bumps over the redistribution layer and connected to the redistribution layer.

First claim

What is claimed is:

1. A device comprising:
a fan-out structure comprising a redistribution layer on a first side of the fan-out structure and a dielectric layer over the redistribution layer;
a first chip over the first side of the fan-out structure, wherein the first chip comprise a plurality of first through vias connected to the redistribution layer;
a second chip over the first chip, wherein the second chip is connected to the first chip; and
a molding compound layer disposed over the first side of the fan-out structure, wherein the first chip and the second chip are embedded in the molding compound layer, and wherein at least one edge of the first chip and the second chip is vertically aligned with an edge of the molding compound layer.

2. The device of claim 1 , further comprising:
a plurality of first bumps over the dielectric layer and on a second side of the fan-out structure.

3. The device of claim 1 , wherein:
the second chip comprises a plurality of semiconductor dies stacked together, and wherein a top surface of the second chip is exposed outside the molding compound layer.

4. The device of claim 1 , wherein:
a rightmost edge of the second chip is vertically aligned with a rightmost edge of the molding compound layer.

5. The device of claim 1 , wherein:
a leftmost edge of the first chip is vertically aligned with a leftmost edge of the molding compound layer.

6. The device of claim 1 , wherein:
a rightmost edge of the second chip is vertically aligned with a rightmost edge of the molding compound layer; and
a leftmost edge of the first chip is vertically aligned with a leftmost edge of the molding compound layer.

7. The device of claim 1 , wherein:
a first centerline of the first chip is not aligned with a second centerline of the second chip.

8. The device of claim 1 , wherein:
the second chip is connected to the first chip through a joint structure.

9. The device of claim 8 , wherein:
the joint structure comprises a plurality of bumps formed between the first chip and the second chip.

10. The device of claim 8 , wherein:
the joint structure is a single bump formed between the first chip and the second chip.

11. A device comprising:
a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer, and wherein at least one edge of the first chip and the second chip is exposed outside the encapsulation layer;
a redistribution layer on a surface of a first side of the encapsulation layer; and
a plurality of conductive bumps over the redistribution layer and connected to the redistribution layer.

12. The device of claim 11 , wherein:
the redistribution layer is connected to active circuits of the first chip and the second chip; and
the redistribution layer extends beyond at least one edge of the first chip and the second chip.

13. The device of claim 11 , further comprising:
a dielectric layer between the plurality of conductive bumps and the first side of the encapsulation layer; and
a plurality of bumps between the first chip and the second chip.

14. The device of claim 11 , wherein:
a top surface of the multi-chip structure is exposed outside a second side of the encapsulation layer.

15. The device of claim 11 , wherein:
an edge of the first chip is aligned with a first edge of the encapsulation layer; and
an edge of the second chip is aligned with a second edge of the encapsulation layer.

16. A method comprising:
attaching a first chip comprising a plurality of stacked semiconductor dies on a carrier through an adhesive layer;
mounting a second chip on the first chip;
forming a molding compound layer over the carrier, wherein the first chip and the second chip are embedded in the molding compound layer, and wherein at least one edge of the first chip and the second chip is vertically aligned with an edge of the molding compound layer;
grinding the molding compound layer until a surface of the second chip is exposed;
forming a redistribution layer on the surface of the second chip; and
forming a plurality of conductive bumps over the redistribution layer.

17. The method of claim 16 , further comprising:
forming the redistribution layer on the surface of the second chip, wherein:
the redistribution layer extends beyond at least one edge of the first chip; and
the redistribution layer extends beyond at least one edge of the second chip.

18. The method of claim 16 , further comprising:
applying a reflow process to the first chip and the second chip so that the second chip is bonded on the first chip through a plurality of bumps to form a multi-chip structure.

19. The method of claim 16 , further comprising:
applying a reflow process to the first chip and the second chip so that the second chip is bonded on the first chip through a single bump to form a multi-chip structure.

20. The method of claim 16 , further comprising:
depositing a dielectric layer on the redistribution layer;
forming a plurality of under bump metallization (UBM) structures in the dielectric layer; and
forming the plurality of conductive bumps over the UBM structures.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yeh Der-Chyang

Classifications

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title