Chip arrangement and a method of manufacturing a chip arrangement

Patent metadata

Field	Value
Publication number	US-9653405-B2
Application number	US-201313771222-A
Country	US
Kind code	B2
Filing date	Feb 20, 2013
Priority date	Feb 20, 2013
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

In various embodiments, a chip arrangement may be provided. The chip arrangement may include a metallic carrier. The chip arrangement may also include at least one chip arranged on the metallic carrier, wherein the at least one chip includes a chip contact, wherein the chip contact is electrically coupled to the metallic carrier. The chip arrangement may also include encapsulation material at least partially encapsulating the at least one chip. The chip arrangement may also include an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier.

First claim

What is claimed is:

1. A chip arrangement, comprising:
a metallic carrier;
at least one chip arranged on the metallic carrier, wherein the at least one chip comprises a chip contact, wherein the chip contact is electrically coupled to the metallic carrier;
encapsulation material at least partially encapsulating the at least one chip; and
an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier;
wherein the electrically conductive shielding structure is formed over a first main surface of the encapsulation material, a first sidewall of the encapsulation material and a sidewall of the metallic carrier, the first sidewall of the encapsulating material and the sidewall of the metallic carrier being in the same plane;
wherein a second sidewall of the encapsulation material, which is opposite the first sidewall of the encapsulation material is substantially free of the electrically conductive shielding structure;
wherein the electrically conductive shielding structure is configured to shield the at least one chip from electromagnetic radiation.

2. The chip arrangement of claim 1 , wherein the metallic carrier is configured to provide a reference potential.

3. The chip arrangement of claim 1 , wherein the chip contact is electrically coupled to the metallic carrier via a wire bond.

4. The chip arrangement of claim 1 , wherein the electrically conductive shielding structure is formed to electrically contact the metallic carrier at the first sidewall of the encapsulation material.

5. The chip arrangement of claim 1 , configured as a leadless package.

6. The chip arrangement of claim 1 , wherein at least one hole is formed through the encapsulation material to expose at least a portion of the metallic carrier;
wherein the electrically conductive shielding structure is formed over at least a portion of a sidewall of the hole through the encapsulation material to electrically contact the exposed portion of the metallic carrier.

7. The chip arrangement of claim 1 , the chip further comprising: a first surface and a second surface opposite the first surface; wherein the chip contact is electrically coupled to the metallic carrier at the second surface; and
wherein electrically conductive shielding structure formed over the first main surface of the encapsulation material is disposed such that the first surface of the chip faces the electrically conductive shielding.

8. The chip arrangement of claim 1 , wherein the electrically conductive shielding structure is formed over an exterior sidewall of the metallic carrier.

9. A chip arrangement, comprising:
a metallic carrier;
at least one chip arranged on the metallic carrier, wherein the at least one chip comprises a chip contact, wherein the chip contact is electrically coupled to the metallic carrier;
encapsulation material at least partially encapsulating the at least one chip, wherein at least a portion of the metallic carrier is free from the encapsulation material; and
an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier via the portion of the metallic carrier which is free from the encapsulation material,
wherein the portion of the metallic carrier which is free from the encapsulation material forms a portion of a sidewall of the chip arrangement; and
wherein the electrically conductive shielding structure is formed over a first main surface of the encapsulation material, a first sidewall of the encapsulation material and a sidewall of the metallic carrier, the first sidewall of the encapsulating material and the sidewall of the metallic carrier being in the same plane,
wherein a second sidewall of the encapsulation material, which is opposite the first sidewall of the encapsulation material is substantially free of the electrically conductive shielding structure,
wherein the electrically conductive shielding structure is configured to shield the at least one chip from electromagnetic radiation.

10. The chip arrangement of claim 9 , wherein the metallic carrier is configured to provide a reference potential.

11. The chip arrangement of claim 9 , wherein the chip contact is electrically coupled to the metallic carrier via a wire bond.

12. The chip arrangement of claim 9 , wherein at least one hole is formed through the encapsulation material to expose at least a portion of the metallic carrier;
wherein the electrically conductive shielding structure is formed over at least a portion of a sidewall of the hole through the encapsulation material to electrically contact the exposed portion of the metallic carrier.

13. A method for manufacturing a chip arrangement, the method comprising:
arranging at least one chip on a metallic carrier, wherein the at least one chip comprises a chip contact;
electrically coupling the chip contact to the metallic carrier;
at least partially encapsulating the at least one chip with encapsulation material; and
forming an electrically conductive shielding structure over at least a portion of the encapsulation material to electrically contact the metallic carrier,
wherein the electrically conductive shielding structure is formed over a first main surface of the encapsulation material, a first sidewall of the encapsulation material and a sidewall of the metallic carrier, the first sidewall of the encapsulating material and the sidewall of the metallic carrier being in the same plane,
wherein a second sidewall of the encapsulation material, which is opposite the first sidewall of the encapsulation material is substantially free of the electrically conductive shielding structure,
wherein the electrically conductive shielding structure is configured to shield the at least one chip from electromagnetic radiation.

Assignees

• Infineon Technologies Ag

Inventors

• Theuss Horst
• See Beng Keh

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title