Compact multi-die power semiconductor package

Patent metadata

Field	Value
Publication number	US-9653386-B2
Application number	US-201414515860-A
Country	US
Kind code	B2
Filing date	Oct 16, 2014
Priority date	Oct 16, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

One disclosed implementation is a power semiconductor package including a sync transistor having a drain on its top surface and a source and a gate on its bottom surface. The source of the sync transistor is configured for attachment to a first partially etched leadframe segment and the gate of the sync transistor is configured for attachment to a second partially etched leadframe segment. A control transistor has a source and a gate on its top surface and a drain on its bottom surface. The drain of the control transistor is configured for attachment to a third partially etched leadframe segment. A first conductive clip extends to the substrate and is situated over the drain of the sync transistor and the source of the control transistor, the first conductive clip coupling the drain of the sync transistor and the source of the control transistor to the substrate without using a leadframe.

First claim

The invention claimed is:

1. A power semiconductor package comprising:
a sync transistor having a drain on a top surface of said sync transistor, and a source and a gate on a bottom surface of said sync transistor;
said source of said sync transistor configured for attachment to a first partially etched leadframe segment and said gate of said sync transistor configured for attachment to a second partially etched leadframe segment;
a control transistor having a source and a gate on a top surface of said control transistor, and a drain on a bottom surface of said control transistor;
said drain of said control transistor configured for attachment to a third partially etched leadframe segment;
a first conductive clip that includes a vertical segment extending to a substrate and a horizontal segment that is perpendicular to said vertical segment and that is situated over said drain of said sync transistor and said source of said control transistor, said first conductive clip coupling said drain of said sync transistor and said source of said control transistor to said substrate by an end surface of said vertical segment without using a leadframe; and
a second conductive clip that includes a vertical segment extending to said substrate and a horizontal segment that is perpendicular to said vertical segment and that is situated over and coupled to said gate of said control transistor, said second conductive clip coupling said gate of said control transistor to said substrate by an end surface of said vertical segment without using a leadframe.

2. The power semiconductor package of claim 1 , wherein said first partially etched leadframe segment, said second partially etched leadframe segment, and said third partially etched leadframe segment are configured for attachment to said substrate.

3. The power semiconductor package of claim 1 , wherein said sync transistor and said control transistor are selected from the group consisting of a FET, an IGBT, and a HEMT.

4. The power semiconductor package of claim 1 , wherein said sync transistor and said control transistor are selected from the group consisting of a silicon FET and a GaN FET.

5. The power semiconductor package of claim 1 , wherein said substrate is a circuit board.

6. The power semiconductor package of claim 1 , wherein said sync transistor and said control transistor are part of a voltage converter.

7. A power semiconductor package comprising:
a sync transistor having a drain on a top surface of said sync transistor, and a source and a gate on a bottom surface of said sync transistor;
said source of said sync transistor attached to a first partially etched leadframe segment and said gate of said sync transistor attached to a second partially etched leadframe segment;
a control transistor having a source and a gate on a top surface of said control transistor, and a drain on a bottom surface of said control transistor;
said drain of said control transistor attached to a third partially etched leadframe segment;
a first conductive clip that includes a vertical segment extending to a substrate and a horizontal segment that is perpendicular to said vertical segment and that is situated over said drain of said sync transistor and said source of said control transistor, said first conductive clip coupling said drain of said sync transistor and said source of said control transistor to said substrate at an end surface of said vertical segment without using a leadframe;
a second conductive clip that includes a vertical segment extending to said substrate and a horizontal segment that is perpendicular to said vertical segment and that is situated over and coupled to said gate of said control transistor, said second conductive clip coupling said gate of said control transistor to said substrate by an end surface of said vertical segment without using a leadframe; and
an integrated circuit attached to a fourth partially etched lead frame segment, said integrated circuit coupled to said gate of said control transistor and to said gate of said sync transistor.

8. The power semiconductor package of claim 7 , wherein said integrated circuit is coupled to said gate of said sync transistor by traces on said substrate.

9. The power semiconductor package of claim 7 , wherein said sync transistor and said control transistor are selected from the group consisting of a FET, an IGBT, and a HEMT.

10. The power semiconductor package of claim 7 , wherein said sync transistor and said control transistor are selected from the group consisting of a silicon FET and a GaN FET.

11. The power semiconductor package of claim 7 , wherein said substrate is a circuit board.

12. The power semiconductor package of claim 7 , wherein said sync transistor, said control transistor, and said integrated circuit are part of a voltage converter.

13. A power semiconductor package comprising:
a plurality of leadframe segments;
a first conductive clip of a power converter, wherein the first conductive clip includes a vertical segment and a horizontal segment;
a second conductive clip of the power converter, wherein the second conductive clip includes a vertical segment and a horizontal segment;
a sync transistor of the power converter, wherein a source node of the sync transistor is mechanically coupled to a first leadframe segment of the plurality of leadframe segments, a gate node of the sync transistor is mechanically coupled to a second leadframe segment of the plurality of leadframe segments and a drain node of the sync transistor is mechanically coupled to the first conductive clip along a surface thereof;
a control transistor of the power converter, wherein a source node of the control transistor is mechanically coupled to the first conductive clip along the surface thereof, a gate node of the control transistor is mechanically coupled to the second conductive clip along a surface thereof and a drain node of the control transistor is mechanically coupled to a third leadframe segment of the plurality of leadframe segments; and
an integrated circuit of the power converter, wherein the integrated circuit is mechanically coupled to a fourth leadframe segment of the plurality of leadframe segments, and is electrically coupled to the gate node of the sync transistor and to the gate node of the control transistor;
wherein the vertical segment of the first conductive clip is configured to extend to a substrate and electrically couple the drain node of the sync transistor and the source node of the control transistor to the substrate by an end surface of the vertical segment of the first conductive clip that is perpendicular to a long axis of the vertical segment of the first conductive clip.

14. The power semiconductor package of claim 13 , wherein the vertical segment of the second conductive clip is configured to extend to the substrate and electrically couple the gate node of the control transistor to the substrate by an end surface of the vertical segment of the second conductive clip that is perpendicular to a long axis of the vertical segment of the second conductive clip.

15. The power semiconductor package of claim 14 , wherein the vertical segment of the first conductive clip is mechanically coupled to the substrate by the end surface of the vertical segment of the first conductive clip, and wherein the vertical segment of the second conductive clip is mechanically coupled to the substrate by the end surface of the vertical segment of the second conductive clip.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07653

  changes in shapes · CPC title

• H10W72/07354

  changes in dispositions · CPC title