Load queue entry reuse for operand store compare history table update

Patent metadata

Field	Value
Publication number	US-9652248-B2
Application number	US-201615252325-A
Country	US
Kind code	B2
Filing date	Aug 31, 2016
Priority date	Feb 13, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.

First claim

What is claimed is:

1. A computer implemented method for load queue entry reuse for operand store compare (OSC) history table update, the method comprising:
issuing a load instruction into an instruction pipeline of a processor;
allocating a load queue entry in a load queue to the load instruction, the load queue entry comprising a valid tag and a keep tag, wherein the valid tag is set and the keep tag is unset in the allocated load queue entry;
determining whether the load instruction has been flushed;
based on the load instruction not being flushed, determining whether the load instruction has been completed;
based on determining the load instruction is completed:
based in the valid tag and the keep tag being set, updating the OSC history table with OSC information corresponding to the load instruction;

deallocating the load queue entry, unsetting the valid tag and unsetting the keep tag;
flushing the load instruction by the instruction pipeline;
based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag in the allocated load queue entry;
reissuing the load instruction into the instruction pipeline;
determining that the allocated load queue entry corresponds to the reissued load instruction;
based on determining that the allocated load queue entry corresponds to the reissued load instruction:
setting the valid tag and leaving the keep tag set in the allocated load queue entry;
completing the reissued load instruction in the instruction pipeline;
based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table with OSC information corresponding to the load instruction;
based on determining that the allocated load queue entry does not correspond to the reissued load instruction:
determining whether the load queue is full:
based on determining that the load queue is full:
identifying a load queue entry in which the valid tag is unset and the keep tag is set;
deallocating the identified load queue entry by unsetting the keep tag in the identified load queue entry;
allocating the deallocated load queue entry to the load instruction;
based on not identifying the load queue entry where the valid tag is unset and the keep tag is set, not entering the issued instruction into the load queue;

based on determining the load queue is not full:
identifying the load queue entry in which the valid tag is unset and the keep tag is unset; and

allocating the identified load queue entry into the load instruction.

Assignees

• IBM

Inventors

• Alexander Khary J
• Granovsky Ilya

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3871 Primary

  Asynchronous instruction pipeline, e.g. using handshake signals between stages · CPC title