Execution Control of a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric
US-2019303147-A1 · Oct 3, 2019 · US
Asynchronous instruction pipeline, e.g. using handshake signals between stages
Asynchronous instruction pipeline, e.g. using handshake signals between stages · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F9/3871 |
| Official title | {Asynchronous instruction pipeline, e.g. using handshake signals between stages} |
| Display label | Asynchronous instruction pipeline, e.g. using handshake signals between stages |
| Total patents | 204 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 15 |
| 2016 | 13 |
| 2017 | 17 |
| 2018 | 9 |
| 2019 | 17 |
| 2020 | 15 |
| 2021 | 42 |
| 2022 | 22 |
| 2023 | 25 |
| 2024 | 15 |
| 2025 | 8 |
| 2026 | 6 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Method and apparatus for a self-clocked, event triggered superscalar processor
US-10372458-B2 · Aug 6, 2019 · US
Energy Efficient Processor Core Architecture for Image Processor
US-2019220282-A1 · Jul 18, 2019 · US
Asynchronous instruction execution apparatus with execution modules invoking external calculation resources
US-10338921-B2 · Jul 2, 2019 · US
System and method for an asynchronous processor with pepelined arithmetic and logic unit
US-10318305-B2 · Jun 11, 2019 · US
Timestamp suppression
US-2019146856-A1 · May 16, 2019 · US
System and method for an asynchronous processor with heterogeneous processors
US-10133578-B2 · Nov 20, 2018 · US
Data Processing Device for Providing Access to a Data Stream
US-2018267808-A1 · Sep 20, 2018 · US
Method and apparatus for asynchronous processor with auxiliary asynchronous vector processor
US-10042641-B2 · Aug 7, 2018 · US
Method and apparatus for asynchronous scheduling
US-2018217844-A1 · Aug 2, 2018 · US
Operation of a multi-slice processor preventing early dependent instruction wakeup
US-9983875-B2 · May 29, 2018 · US
Interface for non-volatile memory
US-2018136878-A1 · May 17, 2018 · US
Load queue entry reuse for operand store compare history table update
US-9928075-B2 · Mar 27, 2018 · US
System and method for an asynchronous processor with token-based very long instruction word architecture
US-9928074-B2 · Mar 27, 2018 · US
Controlling the operating speed of stages of an asynchronous pipeline
US-2018024837-A1 · Jan 25, 2018 · US
Method and apparatus for asynchronous processor pipeline and bypass passing
US-9846581-B2 · Dec 19, 2017 · US
Energy efficient processor core architecture for image processor
US-9772852-B2 · Sep 26, 2017 · US
Operation of a multi-slice processor preventing early dependent instruction wakeup
US-2017255465-A1 · Sep 7, 2017 · US
Energy Efficient Processor Core Architecture for Image Processor
US-2017249153-A1 · Aug 31, 2017 · US
Method and apparatus for asynchronous processor removal of meta-stability
US-9740487-B2 · Aug 22, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F9/3871?
- CPC G06F9/3871 is the Cooperative Patent Classification code for “Asynchronous instruction pipeline, e.g. using handshake signals between stages.”
- How many patents are filed under CPC G06F9/3871 (Asynchronous instruction pipeline, e.g. using handshake signals between stages)?
- Our database includes 204 publications tagged with this CPC code.
- Is patent activity under CPC G06F9/3871 growing?
- Publication counts under this code: 15 in 2024 vs 8 in 2025 (latest complete years).