Chip stack structures that implement two-phase cooling with radial flow

Patent metadata

Field	Value
Publication number	US-9648782-B2
Application number	US-201615041213-A
Country	US
Kind code	B2
Filing date	Feb 11, 2016
Priority date	Aug 30, 2012
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.

First claim

We claim:

1. A method, comprising:
supplying liquid coolant into a central inlet manifold formed through a central region of a chip stack, the chip stack comprising a plurality of conjoined chips disposed on a substrate;
feeding liquid coolant from the central inlet manifold into flow channels that are formed between pairs of conjoined chips in the chip stack, wherein the liquid coolant is fed into the flow channels through inlet nozzles formed along a sidewall of the central inlet manifold of the chip stack, wherein the liquid coolant flows through the flow channels in a direction that is perpendicular to a flow of liquid coolant in the central inlet manifold;
collecting heated liquid vapor that exits out from output ports of the flow channels around an outer periphery of the chip stack,
wherein supplying liquid coolant into the central inlet manifold of the chip stack comprises:
placing a package lid over the chip stack, wherein the package lid covers and encloses the chip stack and contacts the substrate around the outer periphery of the chip stack to define a peripheral output manifold region within an interior region of the package lid which surrounds the outer periphery of the chip stack; and
supplying the liquid coolant through a central inlet of the package lid, wherein the central inlet is aligned to the central inlet manifold of the chip stack to supply liquid coolant to the central inlet manifold; and

wherein collecting the heated liquid vapor comprises collecting the heated liquid vapor though a peripheral outlet of the package lid, wherein the peripheral outlet of the package lid is aligned to the peripheral output manifold region within the interior region of the package lid.

2. The method of claim 1 , further comprising forming the inlet nozzles along the sidewall of the central inlet manifold of the chip stack to have different sizes, wherein an inlet nozzle facing towards a corner region of the chip stack is larger than an inlet nozzle facing towards a side of the chip stack.

3. The method of claim 1 , wherein the flow channels comprise radial flow channels that are defined by forming a radial arrangement of guiding walls in spaces between the pairs of conjoined chips in the chip stack, wherein the guiding walls extend in a radial direction between the central inlet manifold of the chip stack and the outer periphery of the chip stack to guide a flow of liquid and vapor in the radial direction.

4. The method of claim 3 , further comprising forming the guiding walls and inlet nozzles on the surfaces of the chips using a layer of polymer material or metallic material.

5. The method of claim 3 , further comprising forming the guiding walls and inlet nozzles by etching surfaces of the chips to pattern the guiding walls and inlet nozzles.

6. The method of claim 3 , further comprising arranging one or more of the guiding walls to guide a flow of liquid coolant and heated liquid vapor towards a hot spot region in a given region of the chip stack.

7. The method of claim 3 , further comprising arranging one or more of the guiding walls to guide a flow of liquid coolant and heated liquid vapor to a given zone in proportion to a total power density of the given zone or a cooling requirement.

8. The method of claim 3 , further comprising arranging the guiding walls to form radial flow channels that are fed by different inlet nozzles of the central inlet manifold.

9. The method of claim 8 , wherein a cross-sectional area of an inlet nozzle feeding a radial flow channel that extends towards a corner of the chip stack is greater than a cross-sectional area of an inlet nozzle feeding a radial flow channel that extends toward a side of the chip stack.

10. The method of claim 3 , further comprising arranging the guiding walls to form a hierarchical arrangement of radial flow channels.

11. The method of claim 1 , further comprising supplying liquid coolant to a target region of the chip stack through a local input manifold of the chip stack.

12. The method of claim 11 , wherein target region comprises a hot spot of the chip stack.

13. The method of claim 11 , further comprising controllably supplying the liquid coolant to the target region of the chip stack to modulate a local vapor quality at the target region.

14. The method of claim 1 , further comprising forming the chip stack by conjoining adjacent chips in the chip stack using micro solder ball connections.

15. The method of claim 14 , wherein the flow channels are defined, at least in part, by a space between surfaces of two adjacent chips in the chip stack that are conjoined back to back using the micro solder ball connections.

16. The method of claim 15 , wherein the flow channels are further defined, at least in part, by etched channels that are formed in the surfaces of the two adjacent chips.

17. The method of claim 14 , wherein at least some of the micro solder ball connections provide electrical connections between through-silicon vias that are formed in the conjoined adjacent chips.

18. A method, comprising:
supplying liquid coolant into a central inlet manifold formed through a central region of a chip stack, the chip stack comprising a plurality of conjoined chips disposed on a substrate;
feeding liquid coolant into flow channels that are formed between pairs of conjoined chips in the chip stack, wherein the liquid coolant is fed into the flow channels through inlet nozzles formed along a sidewall of the central inlet manifold of the chip stack;
collecting heated liquid vapor that exits out from output ports of the flow channels around an outer periphery of the chip stack;
wherein the flow channels comprise radial flow channels that are defined by forming a radial arrangement of guiding walls in spaces between the pairs of conjoined chips in the chip stack, wherein the guiding walls extend in a radial direction between the central inlet manifold of the chip stack and the outer periphery of the chip stack to guide a flow of liquid and vapor in the radial direction;
wherein the guiding walls are arranged to form a hierarchical arrangement of radial flow channels; and
wherein in the hierarchical arrangement of radial flow channels, a given radial flow channel is divided into at least two separate radial flow channels at some radial distance from a center point of the central input manifold of the chip stack, wherein each of the two separate radial flow channels are fed by different inlet nozzles that are formed in the given radial flow channel.

Assignees

• IBM

Inventors

• Brunschwiler Thomas J
• Colgan Evan G
• Knickerbocker John U
• Michael Bruno
• Ong Chin Lee
• Tsang Cornelia K

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title