Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method

Patent metadata

Field	Value
Publication number	US-9648733-B2
Application number	US-201313861338-A
Country	US
Kind code	B2
Filing date	Apr 11, 2013
Priority date	Jun 28, 2007
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.

First claim

What is claimed is:

1. A multilayer substrate core structure including:
a starting insulating layer having a first side with a first planar surface and an opposite second side with a second planar surface;
a first patterned conductive layer on the first planar surface of the first side of the starting insulating layer, and a second patterned conductive layer on the second planar surface of the second side of the starting insulating layer;
a first supplemental insulating layer on the first patterned conductive layer and on the first planar surface of the first side of the starting insulating layer;
a second supplemental insulating layer on the second patterned conductive layer and on the second planar surface of the second side of the starting insulating layer;
a first supplemental patterned conductive layer on the first supplemental insulating layer;
a second supplemental patterned conductive layer on the second supplemental insulating layer; and
a set of conductive vias provided in corresponding via openings extending from the second supplemental patterned conductive layer to the first supplemental patterned conductive layer, the via openings further extending through the first patterned conductive layer and the second patterned conductive layer, the via openings having a conical configuration providing a wider opening in the first patterned conductive layer than in the second patterned conductive layer, wherein at least one conductive via of the set of conductive vias is in electrical contact with the first and second supplemental patterned conductive layers and with the first and second patterned conductive layers, and wherein the at least one conductive via completely fills the corresponding via opening and has the conical configuration.

2. The substrate core structure of claim 1 , wherein the set of conductive vias include a plated conductive material therein.

3. The substrate core structure of claim 1 , wherein the set of conductive vias includes a skip via.

4. The substrate core structure of claim 1 , wherein the starting insulating layer and the supplemental insulating layer each comprise at least one of a glass epoxy resin and bismaleimide-triazine (BT).

Assignees

• Li Yonggang
• Salama Islam
• Gurumurthy Charan
• Azimi Hamid
• Intel Corp

Inventors

• Li Yonggang
• Salama Islam
• Gurumurthy Charan
• Azimi Hamid

Classifications

• H05K3/426

  initial plating of through-holes in substrates without metal · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K3/429

  Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

• H05K3/0035

  of blind holes, i.e. having a metal layer at the bottom · CPC title

• Y10T29/49126

  Assembling bases · CPC title