Integrated circuits including dummy structures and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9646958-B2
Application number	US-72630910-A
Country	US
Kind code	B2
Filing date	Mar 17, 2010
Priority date	Mar 17, 2010
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An integrated circuit includes a core area. The core area has at least one edge region and a plurality of transistors disposed in the edge region. A plurality of dummy structures are disposed outside the core area and adjacent to the at least one edge region. Each channel of the transistors in a channel width direction faces at least one of the dummy structures.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a boundary region comprising an input/output circuit;
a core area comprising functional elements of the integrated circuit located exclusively in the core area, the boundary region and the core area defining an edge separating, in plan view, the boundary region and the core area;
a plurality of transistors disposed in the core area and adjacent to the edge, the plurality of transistors being functional elements of the integrated circuit; and
a plurality of first gate dummy structures disposed in the boundary region and adjacent to the edge, wherein each transistor of the plurality of transistors comprises a channel having a channel width direction substantially perpendicular to the edge, each channel of the plurality of transistors is aligned with a corresponding first gate dummy structure of the plurality of first gate dummy structures along the channel width direction without an intervening dummy structure therebetween, each element of the boundary region adjacent the edge is a first gate dummy structure of the plurality of first gate dummy structures; and
a plurality of second gate dummy structures, wherein an entirety of each second gate dummy structure of the plurality of second gate dummy structures is farther from the edge than each first gate dummy structure of the plurality of first gate dummy structures, and each second gate dummy structure of the plurality of second gate dummy structures and each first gate dummy structure of the plurality of first gate dummy structures is aligned with a channel of a corresponding transistor of the plurality of transistors in an alternating fashion.

2. The integrated circuit of claim 1 , further comprising a plurality of oxide definition (OD) dummy patterns, wherein each OD dummy pattern of the plurality of OD dummy patterns is between adjacent first gate patterns of the plurality of first gate patterns.

3. The integrated circuit of claim 1 , further comprising:
a plurality of third dummy patterns, wherein the third dummy patterns are disposed in the core area, between two of the plurality of transistors, and substantially aligned with the first gate dummy patterns along the channel width direction.

4. The integrated circuit of claim 3 , wherein the third dummy patterns include at least one selected from the group consisting of oxide definition (OD) dummy patterns, well dummy patterns, gate dummy patterns, and metal dummy patterns.

5. The integrated circuit of claim 1 , further comprising:
a plurality of fourth dummy patterns, wherein the fourth dummy patterns are disposed adjacent to the second gate dummy patterns and misaligned, along the channel width direction, from the second gate dummy patterns.

6. The integrated circuit of claim 5 , wherein the fourth dummy patterns include at least one selected from the group consisting of oxide definition (OD) dummy patterns, well dummy patterns, gate dummy patterns, and metal dummy patterns.

7. The integrated circuit of claim 1 , each transistor of the plurality of transistors further comprises an OD pattern by which the channel thereof is defined.

8. An integrated circuit, comprising:
a boundary region comprising an input/output circuit;
a core area comprising functional elements of the integrated circuit located exclusively in the core area, the boundary region and the core area defining an edge separating, in plan view, the boundary region and the core area;
a plurality of transistors disposed in the core area and adjacent to the edge, the plurality of transistors being functional elements of the integrated circuit;
a plurality of first oxide definition (OD) dummy patterns disposed in the boundary region and adjacent to the edge, wherein adjacent first OD dummy patterns are defined on opposite sides of a first dummy gate; and
a plurality of second OD dummy patterns that are disposed in the boundary region, wherein adjacent second OD dummy patterns are defined on opposite sides of a second dummy gate, the plurality of first OD dummy patterns are closer to the edge than the plurality of second OD dummy patterns, and the plurality of second OD dummy patterns misaligned, along a direction perpendicular to the edge, from the plurality of first OD dummy patterns,
and a center of each second OD dummy pattern of the plurality of second OD dummy patterns and a center of each first OD dummy pattern of the plurality of first OD dummy patterns is aligned with a channel of a corresponding transistor of the plurality of transistors in an alternating fashion.

9. The integrated circuit of claim 8 , further comprising:
a plurality of third OD dummy patterns, wherein each third OD dummy pattern of the third OD dummy patterns is disposed in the core area, between two of the transistors, and substantially aligned with a corresponding first OD dummy pattern of the plurality of first OD dummy patterns along the direction.

10. The integrated circuit of claim 8 , further comprising:
a plurality of fourth OD dummy patterns, wherein each fourth OD dummy pattern of the fourth OD dummy patterns is disposed adjacent to corresponding second OD dummy patterns of the plurality of second OD dummy patterns and misaligned from the second OD dummy patterns along the direction.

11. The integrated circuit of claim 8 , further comprising:
a plurality of first gate dummy patterns, wherein each of the first gate dummy patterns is disposed between two of the first OD dummy patterns.

12. The integrated circuit of claim 11 , further comprising:
a plurality of second gate dummy patterns, wherein each of the second gate dummy patterns is disposed between two of the second OD dummy patterns.

13. An integrated circuit, comprising:
a boundary region comprising an input/output circuit;
a core area comprising functional elements of the integrated circuit located exclusively in the core area, the boundary region and the core area defining an edge separating, in plan view, the boundary region and the core area;
a plurality of transistors disposed in the core area and adjacent to the edge, the plurality of transistors being functional elements of the integrated circuit;
a plurality of first gate dummy patterns disposed in the boundary region and adjacent to the edge, wherein a channel of every transistor of the plurality of transistors in the core area adjacent to the boundary region is aligned with a corresponding gate dummy pattern of the plurality of first gate dummy patterns along a channel width direction without an intervening dummy pattern therebetween; and
a plurality of second dummy patterns disposed in the core area and between a transistor of the plurality of transistors and a single active transistor, wherein the single active transistor is the only active transistor between a periphery of the core region and the plurality of second dummy patterns, and a gate of each dummy pattern of the plurality of second dummy patterns is substantially aligned with a corresponding gate dummy pattern of the plurality of first gate dummy patterns along the channel width direction without an intervening active transistor.

14. The integrated circuit of claim 13 , further comprising a plurality of oxide definition (OD) dummy patterns, wherein each OD dummy pattern of the plurality of OD dummy patterns is between adjacent first gate patterns of the plurality of first gate patterns.

15. The integrated circuit of claim 13 ,
further comprising:
first oxide definition (OD) dummy patterns disposed in the boundary region, wherein a pair of adjacent first OD dummy patterns sandwich one of the first gate dummy patt

Assignees

• Wang Chien-Hsun
• Chang Chih-Sheng
• Meng Hsien-Hui
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chien-Hsun
• Chang Chih-Sheng
• Meng Hsien-Hui

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H01L27/105

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic