Embedded semiconductive chips in reconstituted wafers, and systems containing same

Patent metadata

Field	Value
Publication number	US-9646851-B2
Application number	US-201615070968-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	Apr 2, 2010
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

First claim

What is claimed is:

1. A process of forming a reconstituted wafer, comprising:
disposing a plurality of semiconductive dice above a backing plate, wherein the plurality of semiconductive dice includes a first die and wherein the first die includes at least one terminal on an active surface of the first die;
embedding the plurality of semiconductive dice in a mass, wherein the mass obscures the at least one terminal of the first die, and wherein portions of the mass extend over and contact portions of the first die active surface; and
removing a portion of the mass to expose the at least one terminal of the first die and to form a first surface; and
removing the backing plate.

2. The process of claim 1 , further comprising disposing an adhesive on the backing plate prior to disposing the plurality of semiconductive dice above the backing plate, and further comprising removing the adhesive after removing the portion of the mass.

3. The process of claim 1 , wherein removing a portion of the mass comprises grinding the mass.

4. The process of claim 1 , wherein removing a portion of the mass comprises polishing the mass.

5. The process of claim 1 , wherein removing a portion of the mass comprises grinding followed by polishing.

6. The process of claim 1 , further including cutting at least one of the plurality of semiconductive dice from the plurality of semiconductive dice after removing the backing plate.

7. The process of claim 1 , further including forming metallizations above the first surface to connect to the at least one terminal of the first die.

8. The process of claim 1 , further including forming a bumpless build-up layer (BBUL) above the first surface.

9. The process of claim 1 , further including forming a bumpless build-up layer (BBUL) above the first surface prior to removing the backing plate.

10. The process of claim 9 , further including cutting at least one of the plurality of semiconductive dice from the plurality of semiconductive dice after removing the backing plate.

11. The process of claim 1 , further including forming a bumpless build-up layer (BBUL) above the first surface; and coupling a device to the BBUL and to at least one of the plurality of semiconductive dice, wherein the BBUL is between the device and the plurality of semiconductive dice.

12. The process of claim 1 , further including forming a bumpless build-up layer (BBUL) above the first surface; and coupling a plurality of devices to the BBUL and to at least one of the plurality semiconductive dice, wherein the BBUL is between the plurality of devices and the plurality of semiconductive die, and wherein at least one device of the plurality of devices is a passive device.

13. The process of claim 1 , further wherein embedding the plurality of semiconductive dice in a mass comprises embedding the plurality of semiconductive dice in an epoxy.

14. The process of claim 1 , further wherein embedding the plurality of semiconductive dice in a mass comprises embedding the plurality of semiconductive dice in a material selected from the group consisting of silicones, polyimides, epoxy-acrylates, and liquid crystal polymers.

Assignees

• Intel Corp

Inventors

• Sankman Robert L
• Guzek John S

Classifications

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title