Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

Patent metadata

Field	Value
Publication number	US-9257368-B2
Application number	US-201213996839-A
Country	US
Kind code	B2
Filing date	May 14, 2012
Priority date	May 14, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

First claim

What is claimed is:

1. A microelectronic package, comprising:
a microelectronic device having an active surface and an opposing back surface, and at least one through-silicon via extending into the microelectronic device from the microelectronic device back surface;
a first bumpless build-up layer structure formed adjacent the active surface and at least one side of the microelectronic device, wherein the first bumpless build-up layer structure includes a first surface extending over the microelectronic device active surface and a second surface substantially planar to the microelectronic device back surface;
a second bumpless build-up layer structure abutting the microelectronic device back surface and abutting the first bumpless build-up layer structure second surface;
at least one first package conductive route extending through the first bumpless build-up layer structure, extending through the second bumpless build-up layer structure, and electrically connected to the microelectronic device active surface; and
at least one second package conductive route extending through second bumpless build-up layer structure and electrically connected to at least one microelectronic device through-silicon via.

2. The microelectronic package of claim 1 , wherein a portion of the second bumpless build-up layer structure extends adjacent a portion of the first bumpless build-up layer adjacent the at least one microelectronic device side.

3. The microelectronic package of claim 1 , wherein the microelectronic device further comprises integrated circuitry formed proximate the microelectronic device active surface.

4. The microelectronic package of claim 3 , wherein the at least one microelectronic device through-silicon via comprises at least one microelectronic device through-silicon via extending from the microelectronic device back surface to the microelectronic device integrated circuitry.

5. The microelectronic package of claim 1 , wherein the microelectronic device further comprises an interconnection layer formed proximate the microelectronic device active surface.

6. The microelectronic package of claim 5 , wherein the at least one microelectronic device through-silicon via comprises at least one microelectronic device through-silicon via extending from the microelectronic device back surface to the microelectronic device interconnection layer.

7. The microelectronic package of claim 1 , wherein the at least one first package conductive route comprises at least one first package conductive route through the first bumpless build-up layer structure and the second bumpless build-up layer structure electrically connected to the microelectronic device active surface and at least one external interconnect.

8. The microelectronic package of claim 1 , wherein the at least one second package conductive route comprises at least one second package conductive route through the second bumpless build-up layer structure electrically connected to at least one microelectronic device through-silicon via and at least one external interconnect.

9. The microelectronic package of claim 1 , wherein the microelectronic device comprises a semiconducting substrate having an active surface and a back surface, wherein the semiconducting substrate back surface comprises the microelectronic device back surface, and a microelectronic device interconnection layer adjacent the semiconducting substrate active surface, wherein the microelectronic device interconnection layer comprises the microelectronic device active surface.

10. The microelectronic package of claim 1 , wherein the first bumpless build-up layer structure comprises a silica filled epoxy.

11. The microelectronic package of claim 1 , wherein the second bumpless build-up layer structure comprises a silica filled epoxy.

12. A method of forming a microelectronic package, comprising:
forming a microelectronic device having an active surface and an opposing back surface, and at least one through-silicon via extending into the microelectronic device from the microelectronic device back surface;
forming a first bumpless build-up layer structure adjacent the active surface and at least one side of the microelectronic device, wherein the first bumpless build-up layer structure includes a first surface extending over the microelectronic device active surface and a second surface substantially planar to the microelectronic device back surface;
forming a second bumpless build-up layer structure abutting the microelectronic device back surface and abutting the first bumpless build-up layer structure second surface;
forming at least one first package conductive route extending through the first bumpless build-up layer structure, extending through the second bumpless build-up layer structure, and electrically connected to the microelectronic device active surface; and
forming at least one second package conductive route extending through second bumpless build-up layer structure and electrically connected to at least one microelectronic device through-silicon via.

13. The method of forming the microelectronic package of claim 12 , further comprising forming a portion of the second bumpless build-up layer structure to extend adjacent a portion of the first bumpless build-up layer adjacent the at least one microelectronic device side.

14. The method of forming the microelectronic package of claim 12 , wherein forming the microelectronic device further comprises forming integrated circuitry proximate the microelectronic device active surface.

15. The method of forming the microelectronic package of claim 14 , wherein forming the at least one microelectronic device through-silicon via comprises forming at least one microelectronic device through-silicon via extending from the microelectronic device back surface to the microelectronic device integrated circuitry.

16. The method of forming the microelectronic package of claim 12 , wherein forming the microelectronic device further comprises an interconnection layer proximate the microelectronic device active surface.

17. The method of forming the microelectronic package of claim 16 , wherein forming the at least one microelectronic device through-silicon via comprises forming at least one microelectronic device through-silicon via extending from the microelectronic device back surface to the microelectronic device interconnection layer.

18. The method of forming the microelectronic package of claim 12 , wherein forming the at least one first package conductive route comprises forming at least one first package conductive route through the first bumpless build-up layer structure and the second bumpless build-up layer structure electrically connected to the microelectronic device active surface and at least one external interconnect.

19. The method of forming the microelectronic package of claim 12 , wherein forming the at least one second package conductive route comprises forming at least one second package conductive route through the second bumpless build-up layer structure electrically connected to at least one microelectronic device through-silicon via and at least one external interconnect.

20. The method of forming the microelectronic package of claim 12 , wherein forming the microelectronic device comprises forming a semiconducting substrate having an active surface and a back surface, wherein the semiconducting substrate back surface comprises the microelectronic device back surface, and a microelectronic device interconnection layer adjacent the semiconducting

Assignees

• Goh Eng Huat
• Teoh Hoay Tien
• Intel Corp

Inventors

• Goh Eng Huat
• Teoh Hoay Tien

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title