Active regions with compatible dielectric layers

Patent metadata

Field	Value
Publication number	US-9646822-B2
Application number	US-201615351169-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	Sep 18, 2006
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

First claim

What is claimed is:

1. A method of fabricating a non-planar semiconductor device, the method comprising:
forming a semiconductor fin protruding from and continuous with a bulk crystalline semiconductor substrate;
forming an isolation layer laterally adjacent to a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin extends above the isolation layer, the upper portion of the semiconductor fin having a top surface and laterally adjacent sidewall surfaces;
oxidizing outermost portions of the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin, the oxidizing forming an oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin;
depositing a gate material on the oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin;
patterning the gate material and the oxide layer to form a gate electrode on a gate dielectric layer on a portion of the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin;
removing a portion of the upper portion of the semiconductor fin; and
forming a replacement semiconductor fin upper portion comprising a semiconductor material different than the bulk crystalline semiconductor substrate, wherein the gate dielectric layer is on a channel region of a top surface and laterally adjacent sidewall surfaces of the replacement semiconductor fin upper portion.

2. The method of claim 1 , further comprising:
removing the gate electrode; and
forming a replacement gate electrode above the gate dielectric layer on the channel region of the top surface and laterally adjacent sidewall surfaces of the replacement semiconductor fin upper portion, the replacement gate electrode comprising a metal.

3. The method of claim 2 , further comprising:
subsequent to removing the gate electrode and prior to forming the replacement gate electrode, forming a second gate dielectric layer on the gate dielectric layer, the second gate dielectric layer comprising a high-k material.

4. The method of claim 3 , wherein the second gate dielectric layer is along sidewalls of the replacement gate electrode.

5. The method of claim 1 , further comprising:
removing portions of the replacement semiconductor fin upper portion adjacent to first and second opposite sides of the gate electrode; and
forming replacement source and drain regions comprising a semiconductor material different than the replacement semiconductor fin upper portion.

6. The method of claim 5 , wherein the replacement source and drain regions induce a uniaxial strain to the channel region of the replacement semiconductor fin upper portion.

7. A method of fabricating a non-planar semiconductor device, the method comprising:
forming a silicon fin protruding from and continuous with a bulk crystalline silicon substrate;
forming an isolation layer laterally adjacent to a lower portion of the silicon fin, wherein an upper portion of the silicon fin extends above the isolation layer, the upper portion of the silicon fin having a top surface and laterally adjacent sidewall surfaces;
oxidizing outermost portions of the top surface and laterally adjacent sidewall surfaces of the upper portion of the silicon fin, the oxidizing forming a silicon oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the silicon fin;
depositing a gate material on the silicon oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the silicon fin;
patterning the gate material and the silicon oxide layer to form a gate electrode on a silicon oxide gate dielectric layer on a portion of the top surface and laterally adjacent sidewall surfaces of the upper portion of the silicon fin;
removing a portion of the upper portion of the silicon fin; and
forming a germanium-containing fin upper portion, wherein the silicon oxide gate dielectric layer is on a channel region of a top surface and laterally adjacent sidewall surfaces of the germanium-containing fin upper portion.

8. The method of claim 7 , further comprising:
removing the gate electrode; and
forming a replacement gate electrode above the silicon oxide gate dielectric layer on the channel region of the top surface and laterally adjacent sidewall surfaces of the germanium-containing fin upper portion, the replacement gate electrode comprising a metal.

9. The method of claim 8 , further comprising:
subsequent to removing the gate electrode and prior to forming the replacement gate electrode, forming a second gate dielectric layer on the silicon oxide gate dielectric layer, the second gate dielectric layer comprising a high-k material.

10. The method of claim 9 , wherein the second gate dielectric layer is along sidewalls of the replacement gate electrode.

11. The method of claim 7 , further comprising:
removing portions of the germanium-containing fin upper portion adjacent to first and second opposite sides of the gate electrode; and
forming replacement source and drain regions comprising a semiconductor material different than the germanium-containing fin upper portion.

12. The method of claim 11 , wherein the replacement source and drain regions induce a uniaxial strain to the channel region of the germanium-containing fin upper portion.

13. The method of claim 12 , wherein the uniaxial strain is a compressive uniaxial strain.

14. A method of fabricating a non-planar semiconductor device, the method comprising:
forming a silicon fin protruding from and continuous with a bulk crystalline silicon substrate;
forming an isolation layer laterally adjacent to a lower portion of the silicon fin, wherein an upper portion of the silicon fin extends above the isolation layer, the upper portion of the silicon fin having a top surface and laterally adjacent sidewall surfaces;
oxidizing outermost portions of the top surface and laterally adjacent sidewall surfaces of the upper portion of the silicon fin, the oxidizing forming a silicon oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the silicon fin;
depositing a gate material on the silicon oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the silicon fin;
patterning the gate material and the silicon oxide layer to form a gate electrode on a silicon oxide gate dielectric layer on a portion of the top surface and laterally adjacent sidewall surfaces of the upper portion of the silicon fin;
removing a portion of the upper portion of the silicon fin; and
forming a group III-V material fin upper portion, wherein the silicon oxide gate dielectric layer is on a channel region of a top surface and laterally adjacent sidewall surfaces of the group III-V material fin upper portion.

15. The method of claim 14 , further comprising:
removing the gate electrode; and
forming a replacement gate electrode above the silicon oxide gate dielectric layer on the channel region of the top surface and laterally adjacent sidewall surfaces of the group III-V material fin upper portion, the replacement gate electrode comprising a metal.

16. The method of claim 15 , further comprising:
subsequent to removing the gate electrode and prior to forming the replacement gate electrode, forming a second gate dielectric layer on the silicon oxide gate dielectric layer, the second gate dielectric layer comprising a high-k material.

17. The method of c

Assignees

• Ranade Pushkar
• Intel Corp

Inventors

• Ranade Pushkar

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10P14/69398

  the material having a perovskite structure, e.g. BaTiO3 · CPC title

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title