Memory systems including nonvolatile memory devices and dynamic access methods thereof

Patent metadata

Field	Value
Publication number	US-9646705-B2
Application number	US-201414287580-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	Jun 12, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based on the determined erase mode.

First claim

What is claimed is:

1. A method of reading data from a memory block of a memory device, the method comprising:
detecting a write mode of the memory block in response to a request to read data from the memory block, the detected write mode being one of (i) a first write mode from among a plurality of first write modes and (ii) a second write mode from among a plurality of second write modes, wherein
each of the plurality of first write modes has a corresponding first plurality of incremental step pulse programming states,
each of the plurality of second write modes has a corresponding second plurality of incremental step pulse programming states, and
for each of the plurality of second write modes, verification voltages associated with the second plurality of incremental step pulse programming states decrease as increments between the second plurality of incremental step pulse programming states decrease;

setting a read voltage based on the detected write mode of the memory block; and
reading the data from the memory block using the set read voltage.

2. The method of claim 1 , wherein:
the read voltage is a pass read voltage;
the detected write mode includes a plurality of write mode levels, each of the plurality of write mode levels being associated with a different pass read voltage; and
the setting the read voltage includes,
selecting a write mode level from among the plurality of write mode levels, and
setting the pass read voltage for the memory block based on the selected write mode level.

3. The method of claim 1 , wherein:
the detected write mode includes a plurality of write mode levels, each of the plurality of write mode levels being associated with at least one different read voltage, and
the setting the read voltage includes,
selecting a write mode level from among the plurality of write mode levels, and
setting the read voltage for the memory block based on the selected write mode level.

4. The method of claim 1 , wherein each of the plurality of write mode levels is associated with a same pass voltage.

5. A memory system comprising:
a non-volatile memory including a memory block; and
a storage controller configured to,
detect a write mode of the memory block in response to a request to read data from the memory block, the detected write mode being one of (i) a first write mode from among a plurality of first write modes and (ii) a second write mode from among a plurality of second write modes, wherein
each of the plurality of first write modes has a corresponding first plurality of incremental step pulse programming states,
each of the plurality of second write modes has a corresponding second plurality of incremental step pulse programming states,
for each of the plurality of second write modes, verification voltages associated with the second plurality of incremental step pulse programming states decrease as increments between the second plurality of incremental step pulse programming states decrease,

set a read voltage based on the detected write mode of the memory block, and
read the data from the memory block using the set read voltage.

6. The memory system of claim 5 , wherein:
the read voltage is a pass read voltage;
the detected write mode includes a plurality of write mode levels, each of the plurality of write mode levels being associated with a different pass read voltage; and
the storage controller is further configured to,
select a write mode level from among the plurality of write mode levels, and
set the pass read voltage for the memory block based on the selected write mode level.

Assignees

• Moon Sangkwon
• Kim Kyung Ho
• Kim Jihong
• Jeong Jaeyong
• Samsung Electronics Co Ltd
• Snu R&Db Foundation

Inventors

• Moon Sangkwon
• Kim Kyung Ho
• Kim Jihong
• Jeong Jaeyong

Classifications

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title