Memory devices having source lines directly coupled to body regions and methods
US-2024386966-A1 · Nov 21, 2024 · US
Non-volatile memory apparatus and erasing method thereof
US9196367B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9196367-B2 |
| Application number | US-201414295358-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 4, 2014 |
| Priority date | Apr 2, 2014 |
| Publication date | Nov 24, 2015 |
| Grant date | Nov 24, 2015 |
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Abstract
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The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
First claim
Opening claim text (preview).
What is claimed is: 1. A non-volatile memory apparatus, comprising: a plurality of first memory sectors, disposed in a first well, wherein, each of the first memory sectors comprises a plurality of memory cells for respectively receiving a plurality of control line signals; and a control voltage provider, coupled to the first memory sectors for providing the control line signals to the memory cells of each of the first memory sectors, wherein, when an erasing operation is oper…
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Electricity · mapped topic
Physics · mapped topic
- G11C16/14Primary
Physics · mapped topic
- H03K19/018514Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9196367B2 cover?
- The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provi…
- Who is the assignee on this patent?
- Ememory Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/14. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).