Delivering interrupts through non-transparent bridges in a PCI-express network

Patent metadata

Field	Value
Publication number	US-9645956-B2
Application number	US-201615287985-A
Country	US
Kind code	B2
Filing date	Oct 7, 2016
Priority date	Nov 18, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

First claim

The invention claimed is:

1. A management CPU in a PCI Express (PCIe) network, comprising:
a memory;
a processor for managing initialization of a plurality of I/O devices coupled to a PCIe fabric of the management CPU, wherein the PCIe fabric includes a non-transparent bridge (NTB) through which the PCIe fabric is coupled to a worker CPU of the PCIe network;
the processor being configured to perform operations of:
receiving a request from the worker CPU to enable a first I/O device in the PCIe fabric of the management CPU to send a first interrupt to the worker CPU, wherein the worker CPU has assigned a target interrupt register address for receiving the first interrupt;
mapping the target interrupt register address to a mapped interrupt register address for use by the first I/O device in the PCIe fabric of the management CPU to sent the first interrupt to the worker CPU through the NTB; and
sending an instruction to the first I/O device to register the mapped interrupt register address for the first interrupt in a I/O interrupt vector table of the first I/O device.

2. The management CPU of claim 1 , wherein the processor is further configured for determining, prior to sending the instruction to the first I/O device, whether space is available in the I/O interrupt vector table of the first I/O device for registering the mapped interrupt register address for the first interrupt.

3. The management CPU of claim 1 , wherein the processor is further configured for receiving from the worker CPU information related to a size of a target interrupt register of the worker CPU.

4. The management CPU of claim 1 , wherein the processor is further configured for sending an instruction to the I/O device to enable the first interrupt in the first I/O device, and sending a notification to the worker CPU indicating that the first interrupt has been enabled in the first I/O device.

5. The management CPU of claim 1 , wherein the first interrupt is a Message Signaled Interrupts eXtended (MSI-X) interrupt.

6. A PCI Express (PCIe) network, comprising:
a management CPU;
a worker CPU;
a PCIe fabric of the management CPU, the PCIe fabric comprising a plurality of I/O devices and a non-transparent bridge (NTB) through which the PCIe fabric is coupled to the worker CPU;
the management CPU is configured to perform operations of:
receiving a request from the worker CPU to enable a first I/O device in the PCIe fabric of the management CPU to send a first interrupt to the worker CPU, wherein the worker CPU has assigned a target interrupt register address for receiving the first interrupt;
mapping the target interrupt register address to a mapped interrupt register address for use by the first I/O device in the PCIe fabric of the management CPU to sent the first interrupt to the worker CPU through the NTB; and
sending an instruction to the first I/O device to register the mapped interrupt register address for the first interrupt in a I/O interrupt vector table of the first I/O device.

7. The PCIe network of claim 6 , wherein the management CPU is further configured for determining, prior to sending the instruction to the first I/O device, whether space is available in the I/O interrupt vector table of the first I/O device for registering the mapped interrupt register address for the first interrupt.

8. The PCIe network of claim 6 , wherein the management CPU is further configured for receiving from the worker CPU information related to a size of a target interrupt register of the worker CPU.

9. The PCIe network of claim 6 , wherein the management CPU is further configured for sending an instruction to the I/O device to enable the first interrupt in the first I/O device, and sending a notification to the worker CPU indicating that the first interrupt has been enabled in the first I/O device.

10. The PCIe network of claim 6 , wherein the first interrupt is a Message Signaled Interrupts eXtended (MSI-X) interrupt.

11. A method performed by a management CPU in a PCI Express (PCIe) network, comprising:
receiving a request from a worker CPU in the PCIe network to enable a first I/O device in a PCIe fabric of the management CPU to send a first interrupt to the worker CPU, wherein the PCIe fabric of the management CPU includes a non-transparent bridge (NTB) through which the PCIe fabric is coupled to the worker CPU, and wherein the worker CPU has assigned a target interrupt register address for receiving the first interrupt;
mapping the target interrupt register address to a mapped interrupt register address for use by the first I/O device in the PCIe fabric of the management CPU to sent the first interrupt to the worker CPU through the NTB; and
sending an instruction to the first I/O device to register the mapped interrupt register address for the first interrupt in a I/O interrupt vector table of the first I/O device.

12. The method of claim 11 , further comprising:
determining, by the management CPU prior to sending the instruction to the first I/O device, whether space is available in the I/O interrupt vector table of the first I/O device for registering the mapped interrupt register address for the first interrupt.

13. The method of claim 11 , wherein the step of receiving the request from the worker CPU comprises receiving information related to a size of a target interrupt register of the worker CPU.

14. The method of claim 11 , further comprising:
sending an instruction to the I/O device to enable the first interrupt in the first I/O device, and sending a notification to the worker CPU indicating that the first interrupt has been enabled in the first I/O device.

15. The method of claim 11 , wherein the first interrupt is a Message Signaled Interrupts eXtended (MSI-X) interrupt.

Assignees

• Futurewei Technologies Inc

Inventors

• Egi Norbert
• Lasater Robert
• Boyle Thomas
• Peters John
• Shi Guangyu

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/404

  with address mapping · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4068

  Electrical coupling · CPC title