Imaging device

Patent metadata

Field	Value
Publication number	US-9641784-B2
Application number	US-201514946545-A
Country	US
Kind code	B2
Filing date	Nov 19, 2015
Priority date	Dec 3, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

An object of the present invention is to reduce capacitance of a charge accumulation part (floating diffusion) of each pixel unit. In an imaging device, in addition to a plurality of first switching transistors for coupling a plurality of coupling wires extending in the column direction, a second switching transistor is provided between each of the coupling wires and a floating diffusion in each pixel unit. Preferably, the gate of the first switching transistor and the gate of the second switching transistor are electrically coupled to each other.

First claim

The invention claimed is:

1. An imaging device comprising a plurality of pixel units arranged along a first direction,
wherein each of the pixel units includes
one or plural photoelectric converting elements and
a charge accumulation part to which charges generated by the one or plural photoelectric converting elements are transferred,
wherein the imaging device further comprises
a plurality of coupling switching units provided in correspondence with at least apart of the plurality of pixel units and each having first to third nodes, and
a plurality of coupling lines coupled via the plurality of coupling switching units and extending in the first direction,
wherein the first node is coupled to the charge accumulation part in the corresponding pixel unit,
wherein the second and third nodes are coupled to the adjacent coupling lines, and
wherein each of the coupling switching units is configured to electrically couple or electrically isolate the first to third nodes in response to a control signal.

2. The imaging device according to claim 1 , further comprising an output signal line extending in the first direction,
wherein each of the pixel units further includes:
one or plural transfer transistors corresponding to the one or plural photoelectric converting elements and each coupled between the corresponding photoelectric converting element and the charge accumulation part;
an amplification transistor for amplifying voltage of the charge accumulation part; and
a selection transistor coupled between the amplification transistor and the output signal line.

3. The imaging device according to claim 2 , wherein the plurality of coupling switching units are provided for the plurality of pixel units, respectively, and
wherein each of the pixel units further includes a reset transistor coupled between the coupling line coupled to the second node and a power supply node.

4. The imaging device according to claim 3 , further comprising a vertical scanning circuit controlling the coupling switching unit, the one or plural transfer transistors, the selection transistor, and the reset transistor by a plurality of control signal lines extending in a second direction which crosses the first direction,
wherein before charges accumulated in the photoelectric converting element to be read are transferred to the charge accumulation part via a corresponding transfer transistor, in a state the first to third nodes of the coupling switching unit are electrically coupled, the vertical scanning circuit sets the reset transistor to an on state, thereby performing a reset process of ejecting the charges accumulated in the charge accumulation part.

5. The imaging device according to claim 4 , wherein the imaging device has first and second operation modes,
wherein in the first operation mode, after the reset process, in a state where the first to third nodes of the coupling switching unit are electrically isolated, the vertical scanning circuit transfers charges accumulated in the photoelectric converting element to be read to the charge accumulation part via the corresponding transfer transistor, and outputs a voltage level of the charge accumulation part after the transfer to the output signal line via the selection transistor, and
wherein in the second operation mode, after the reset process, in a state where the first to third nodes of the coupling switching unit are electrically coupled, the vertical scanning circuit transfers charges accumulated in the photoelectric converting element to be read to the charge accumulation part via the corresponding transfer transistor, and outputs a voltage level of the charge accumulation part after the transfer to the output signal line via the selection transistor.

6. The imaging device according to claim 4 , wherein the vertical scanning circuit outputs, after the reset process, a first noise level of the charge accumulation part to the output signal line via the selection transistor in a state where the first to third nodes of the coupling switching unit are electrically coupled,
after that, outputs a second noise level of the charge accumulation part to the output signal line via the selection transistor in a state where the first to third nodes of the coupling switching unit are electrically isolated,
after that, transfers charges accumulated in the photoelectric converting element to be read to the charge accumulation part via a corresponding transfer transistor in a state where the first to third nodes of the coupling switching unit are electrically isolated and outputs a first voltage level of the charge accumulation part after the transfer to the output signal line via the selection transistor, and
after that, outputs a second voltage level of the charge accumulation part to the output signal line via the selection transistor in a state where the first to third nodes of the coupling switching unit are electrically coupled.

7. The imaging device according to claim 6 , further comprising a column circuit coupled to the output signal line,
wherein the column circuit includes
a first A/D converting circuit A/D (Analog to Digital) converting the first noise level and the second voltage level and
a second A/D converting circuit A/D converting the second noise level and the first voltage level.

8. The imaging device according to claim 1 , further comprising first and second all reset transistors coupled between ends of coupling lines at both ends of the plurality of coupling lines and a power supply node.

9. The imaging device according to claim 1 , wherein a pixel unit which is not provided with the plurality of coupling switching units includes a switching transistor for coupling the charge accumulation part and any one of the plurality of coupling lines.

10. The imaging device according to claim 1 , wherein the coupling switching unit includes
a first switching transistor coupled between the first and second nodes and
a second switching transistor coupled between the second and third nodes, and
wherein a control electrode of the first switching transistor and a control electrode of the second switching transistor are mutually coupled.

11. The imaging device according to claim 10 , wherein the coupling switching unit further includes a third switching transistor coupled between the first and third nodes, and
wherein a control electrode of the third switching transistor is electrically mutually coupled to the control electrodes of the first and second switching transistors.

12. The imaging device according to claim 10 , wherein the coupling switching unit includes
a first switching transistor coupled between the first and second nodes and
a second switching transistor coupled between the first and third nodes, and
wherein a control electrode of the first switching transistor and a control electrode of the second switching transistor are mutually coupled.

13. The imaging device according to claim 3 , wherein the imaging device is formed on a semiconductor substrate,
wherein each of the pixel units includes, as the one or plural photoelectric converting elements, first and second photodiodes, the first and second photodiodes are arranged so as to be lined in the first direction,
wherein the charge accumulation part is arranged between the first and second photodiodes,
wherein the coupling switching unit is arranged adjacent to the charge accumulation part in a second direction crossing the first direction,
wherein the amplification transistor is arranged on the side opposite to the coupling switching unit while sandwiching the charge accumulation part, and
wherein the reset transistor and the sel

Assignees

• Renesas Electronics Corp

Inventors

• Suzuki Atsushi

Classifications

• H04N25/709 Primary

  Circuitry for control of the power supply · CPC title

• H04N25/46 Primary

  by combining or binning pixels · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/65

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title