Solid-state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9357148-B2
Application number	US-201514857535-A
Country	US
Kind code	B2
Filing date	Sep 17, 2015
Priority date	Jan 15, 2009
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4×n pixels (where, n is a positive integer), respectively, in horizontal and vertical directions.

First claim

What is claimed is:

1. An imaging device comprising:
a first structural unit including a first array of photodiodes in column and row directions, the first structural unit including:
a first floating diffusion;

a second structural unit including a second array of photodiodes in column and row directions, the second structural unit including:
a second floating diffusion;
an amplification transistor and a select transistor located between and interconnected to the first structural unit and the second structural unit; and
a reset transistor power supply wire connected to a first terminal of a reset transistor, a reset wire connected to a gate electrode of the reset transistor, and a readout wire connected to a gate electrode of a transfer transistor that are disposed in the row direction.

2. The imaging device according to claim 1 , wherein, the amplification transistor and the select transistor are disposed along a side of the first structural unit.

3. The imaging device according to claim 1 , further comprising a connection wiring that is connected to a gate electrode of the amplification transistor and the first floating diffusion, the connection wiring being disposed in the column direction.

4. The imaging device according to claim 1 , further comprising a vertical signal line connected to a first terminal of the amplification transistor and an amplification transistor power supply wire connected to a second terminal of the amplification transistor that are disposed in the column direction.

5. The imaging device according to claim 1 , further comprising a first dummy wiring and a second dummy wiring that extend in the column direction, wherein at least one of the photodiodes is disposed between the first and second dummy wirings.

6. The imaging device according to claim 1 , wherein the first structural unit and the second structural unit have a four-layer wiring structure and a poly layer.

7. The imaging device according to claim 6 , wherein the gate electrode of the reset transistor, a gate electrode of the amplification transistor gate, and a gate electrode of the select transistor are formed in the poly layer.

8. The imaging device according to claim 6 , wherein the reset transistor power supply wire connected to the first terminal of the reset transistor, the reset wire connected to the gate electrode of the reset transistor, and the readout wire connected to the gate electrode of the transfer transistor are in the second wiring layer of the four-layer wiring structure closest to the poly layer.

9. The imaging device according to claim 3 , wherein the first structural unit and the second structural unit have a four-layer wiring structure and a poly layer, and the connection wiring is in the metal layer of the four-layer wiring structure closest to the poly layer.

10. The imaging device according to claim 4 , wherein the first structural unit and the second structural unit have a four-layer wiring structure and a poly layer and the vertical signal line connected to the first terminal of the amplification transistor and the amplification transistor power supply wire connected to the second terminal of the amplification transistor are in the third metal layer of the four-layer wiring structure closest to the poly layer.

11. An electronic apparatus comprising:
an imaging device including:
a first structural unit including a first array of photodiodes in column and row directions, the first structural unit including:
a first floating diffusion;

a second structural unit including a second array of photodiodes in column and row directions, the second structural unit including:
a second floating diffusion;
an amplification transistor and a select transistor located between and interconnected to the first structural unit and the second structural unit; and
a reset transistor power supply wire connected to a first terminal of a reset transistor, a reset wire connected to a gate electrode of the reset transistor, and a readout wire connected to a gate electrode of a transfer transistor that are disposed in the row direction.

12. The electronic apparatus according to claim 11 , wherein, the amplification transistor and the select transistor are disposed along a side of the first structural unit.

13. The electronic apparatus according to claim 11 , further comprising a connection wiring that is connected to a gate electrode of the amplification transistor and the first floating diffusion, the connection wiring being disposed in the column direction.

14. The electronic apparatus according to claim 11 , further comprising a vertical signal line connected to a first terminal of the amplification transistor and an amplification transistor power supply wire connected to a second terminal of the amplification transistor that are disposed in the column direction.

15. The electronic apparatus according to claim 11 , further comprising a first dummy wiring and a second dummy wiring that extend in the column direction, wherein at least one of the photodiodes is disposed between the first and second dummy wirings.

16. The electronic apparatus according to claim 11 , wherein the first structural unit and the second structural unit have a four-layer wiring structure and a poly layer.

17. The electronic apparatus according to claim 16 , wherein the gate electrode of the reset transistor, a gate electrode of the amplification transistor, and a gate electrode of the select transistor are formed in the poly layer.

18. The electronic apparatus according to claim 16 , wherein the reset transistor power supply wire connected to the first terminal of the reset transistor, the reset wire connected to the gate electrode of the reset transistor, and the readout wire connected to the gate electrode of the transfer transistor are in the second wiring layer of the four-layer wiring structure closest to the poly layer.

19. The electronic apparatus according to claim 13 , wherein the first structural unit and the second structural unit have a four-layer wiring structure and a poly layer, and the connection wiring is in the metal layer of the four-layer wiring structure closest to the poly layer.

20. The electronic apparatus according to claim 14 , wherein the first structural unit and the second structural unit have a four-layer wiring structure and a poly layer and the vertical signal line connected to the first terminal of the amplification transistor and the amplification transistor power supply wire connected to the second terminal of the amplification transistor are in the third metal layer of the four-layer wiring structure closest to the poly layer.

Assignees

• Sony Corp

Inventors

• Itonaga Kazuichiro
• Matsumoto Shizunori

Classifications

• H04N25/136

  using complementary colours · CPC title

• H04N25/60

  Noise processing, e.g. detecting, correcting, reducing or removing noise · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/134

  based on three different wavelength filter elements · CPC title

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title