Circuits and methods for decoding amplitude modulated data signals from large amplitude sine wave carrier

Patent metadata

Field	Value
Publication number	US-9641369-B2
Application number	US-201514723687-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	May 29, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A digital load side transmission lighting control apparatus has at one least control gear for controlling at least one lighting source. The control gear includes a period timer to establish an inter-transition time period between each transition within each data packet frame. An inter-transition comparator is in communication with the period timer and configured to compare each of the inter-transition periods with valid inter-transition periods between each transition of the bi-phase encoded data for determining if the inter-transition periods represent valid patterns or are an error has occurred. A data extractor is configured to receive valid bi-phase encoded data from the inter-transition comparator for extracting transmitted data from within the data packet frames. A command formatter is configured to receive the extracted frame data from the data extractor for assembling the telegram bit data pattern for transfer for the subsequent processing.

First claim

What is claimed is:

1. A decoding circuit configured for assembling telegram data patterns from multiple encoded digital data frames demodulated from a low frequency, large amplitude carrier signal modulated with higher frequency, multiple encoded digital data frames, the decoding circuit comprising:
a period timer to establish an inter-transition time period between each transition within each of the multiple encoded digital data frames wherein, the inter-transition time period is the time between each transition of the encoded digital data frames between a first data level and a second data level and between the second data level and the first data level;
an inter-transition comparator in communication with the period timer and configured to compare each of the inter-transition time periods with valid inter-transition time periods between each transition of the encoded digital data frames for determining when the inter-transition time periods represent valid data frame patterns or are an error;
a data extractor configured to receive valid encoded digital data frames from the inter-transition comparator for extracting transmitted digital data frames from within the valid data encoded digital data frames; and
a command formatter configured to receive the extracted digital data frames from the data extractor for assembling the telegram data patterns for transfer for subsequent processing.

2. The decoding circuit of claim 1 wherein the period timer comprises a first counter and a second counter, wherein the first and second counters receive a faster counter clock than a basic frequency of the encoded digital data frames such that each of the first and second counters determines an accurate representation of the inter-transition time periods.

3. The decoding circuit of claim 2 wherein the first counter receives each of the extracted encoded digital data frames, detects, and counts the data of the first data level, and the second counter receives each of the extracted encoded digital data frames, detects, and counts the data of the second data level.

4. The decoding circuit of claim 2 wherein each inter-transition time period transmitted to the inter-transition comparator is compared with maximum and minimum transition time periods to determine a data bit pattern contained in each of the extracted encoded digital data frames.

5. The decoding circuit of claim 4 wherein each telegram data pattern has unique inter-transition time periods that the inter-transition comparator uses to determine a valid data frame pattern for each of the extracted encoded digital data frames decoded.

6. The decoding circuit of claim 4 wherein the inter-transition comparator is programmed with the maximum and minimum transition time periods for each of the valid data frame patterns.

7. The decoding circuit of claim 4 wherein when the received inter-transition time periods fall outside the maximum or minimum transition counts, the inter-transition comparator declares an error and the decoding circuit awaits a start of a new telegram data pattern.

8. The decoding circuit of claim 1 wherein the data extractor decodes the valid encoded digital data frames to extract the telegram data pattern based on a sequence of expected valid bit patterns.

9. The decoding circuit of claim 8 wherein when the data extractor receives an invalid bit pattern an error is declared and the decoding circuit awaits a start of a new telegram data pattern.

10. The decoding circuit of claim 1 wherein the command formatter assembles the telegram data pattern by receiving a “start-of-telegram” symbol that indicates that a series of encoded digital data frames are being transmitted to communicate the telegram data pattern.

11. The decoding circuit of claim 1 wherein the command formatter initializes a telegram register and at the reception of each of the subsequent telegram data, the command formatter places each of the telegram data patterns in the telegram register.

12. The decoding circuit of claim 11 wherein when the telegram register is loaded, the command formatter determines that there are no framing errors, length errors, or parity errors and then transfer the telegram from the telegram register for subsequent processing.

13. The decoding circuit of claim 12 wherein when there are framing errors, length errors, or parity errors, the command formatter declares an error and the decoding circuit a start of a new telegram data pattern.

14. A method for determining telegram data patterns from multiple data packet frames containing valid bi-phase encoded data for subsequent processing, comprising the steps of:
a) determining that a data transition from a first data level to a second data level and between the second data level and the first data level has arrived;
b) determining inter-transition time periods between all the transitions between the first data level and the second data level of each of the multiple data packet frames;
c) comparing each of the inter-transition time periods with valid inter-transition time periods to determine a valid bi-phase encoded data is contained in each of the multiple data packet frames;
d) extracting the telegram data pattern from valid bi-phase encoded data based on a sequence of expected valid bit patterns;
e) determining if an invalid telegram data pattern has been extracted;
f) when an invalid telegram data pattern is determined, declaring an error and awaiting a start of new multiple data packet frames;
g) when the telegram data pattern is determined to be valid, placing the telegram data pattern in a telegram register;
h) repeating steps a) through g) until the telegram register is filled.

15. The method for determining the telegram data pattern of claim 14 further comprising the step of examining the telegram data pattern resident in the telegram register for determining that there are no framing errors, length errors, or parity errors.

16. The method for determining the telegram data pattern of claim 15 further comprising the step of transferring the data resident in the telegram register to associated circuitry for execution of a command indicated by the telegram data pattern, when there are no framing errors, length errors, or parity errors.

17. The method for determining the telegram data pattern of claim 16 further comprising the steps of declaring an error and awaiting a start of a new telegram data pattern, when there are framing errors, length errors, or parity errors.

18. A digital load side transmission lighting control apparatus comprising:
at least one control gear for controlling at least one lighting source and configured for extracting a telegram data pattern from multiple valid encoded digital data frames demodulated from an alternating current (AC), mains voltage modulated with higher frequency multiple encoded digital data frames, the control gear comprising:
a period timer to establish an inter-transition time period between each transition within each of the multiple valid encoded digital data frames wherein, the inter-transition time period is the time between transitions of the valid encoded digital data frames between a first data level to a second data level and between the second data level and the first data level,
an inter-transition comparator in communication with the period timer and configured to compare each of the inter-transition time periods with valid inter-transition time periods for the valid encoded digital data frames for determining when the inter-transition time periods represent valid patterns or are an error;
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Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Tyrrell Julian

Classifications

• H05B45/10

  Controlling the intensity of the light · CPC title

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H05B47/185

  via power line carrier transmission · CPC title

• H05B37/0263

  Electricity · mapped topic

• H04L27/2337 Primary

  using digital techniques to measure the time between zero-crossings · CPC title