Single channel receiver and receiving method

Patent metadata

Field	Value
Publication number	US-11539389-B2
Application number	US-201917281581-A
Country	US
Kind code	B2
Filing date	Nov 28, 2019
Priority date	Nov 29, 2018
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A single channel receiver includes an input terminal that receives an analog input signal, a mixer that down-mixes the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and shifts complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital-converter that converts the intermediate analog signal into an intermediate digital signal, a demodulator that demodulates the intermediate digital signal into a digital output signal, a phase tracking loop that detects zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator that generates the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal with the phase error information.

First claim

The invention claimed is:

1. A single channel receiver comprising:
an input terminal configured to receive an analog input signal,
an RF mixer configured to down-mix the analog input signal to an intermediate frequency by use of a phase- and/or frequency-corrected oscillator frequency signal and to shift complex-valued information contained in the analog input signal only to a real part, or only to an imaginary part to obtain an intermediate real-valued analog signal,
an analog-to-digital-converter configured to convert the intermediate real-valued analog signal into an intermediate digital signal,
a demodulator configured to demodulate the intermediate digital signal into a digital output signal,
a phase tracking loop configured to detect zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, wherein the phase tracking loop includes a zero-crossing detector configured to detect a timing of zero-crossings between two consecutive symbols of the intermediate digital signal,
a timing tracking loop configured to detect signal shape distortions in the digital output signal to obtain timing error information representing a sample timing error in the digital output signal, and
an oscillator configured to generate the phase- and/or frequency-corrected oscillator frequency signal by use of the phase error information,
wherein the timing tracking loop includes a decision-directed phase error detector configured to compare amplitudes of the digital output signal at predetermined timings between two consecutive symbols of the digital output signal,
wherein a first output of the demodulator is provided as a first input to the zero-crossing detector of the phase tracking loop,
wherein a second output of the demodulator is provided as a first input to the decision-directed phase error detector of the timing tracking loop, and wherein an output of the decision-directed phase error detector of the timing tracking loop is provided as a second input to the demodulator.

2. The single channel receiver as claimed in claim 1 , wherein the zero-crossing detector is configured to determine that there is no phase offset in a first case where the zero-crossing is in the middle between the two consecutive symbols and to determine that there is a phase offset in a second case where the zero-crossing is not arranged in the middle between the two subsequent symbols.

3. The single channel receiver as claimed in claim 2 , wherein the zero-crossing detector is configured to determine an amount of the phase offset by detecting a position of the zero-crossing between the two consecutive symbols.

4. The single channel receiver as claimed in claim 3 , wherein the zero-crossing detector is configured to determine the amount of the phase offset based on amplitudes of the two consecutive symbols.

5. The single channel receiver as claimed in claim 4 , wherein the zero-crossing detector is configured to determine the amount of the phase offset by comparing and normalizing the amplitudes of the two consecutive symbols to an expected amplitude value to obtain a timing offset value which is proportional to the phase error.

6. The single channel receiver as claimed in claim 1 , wherein the phase tracking loop further includes a loop filter configured to control phase error compensation.

7. The single channel receiver as claimed in claim 1 , wherein the RF mixer is configured to shift the complex-valued information of the analog input signal to the real part or the imaginary part, respectively, by binary phase shift keying.

8. The single channel receiver as claimed in claim 1 , wherein the decision-directed phase error detector is configured to compare amplitudes of the digital output signal after a quarter and after three quarters of a time period between two consecutive symbols of the digital output signal and/or to compare average amplitudes of the digital output signal at predetermined timing periods between the two consecutive symbols of the digital output signal.

9. The single channel receiver as claimed in claim 1 , wherein the demodulator includes a first down-converter configured to down-convert the sampling rate of the intermediate digital signal and/or to re-sample to a fractional sampling rate.

10. The single channel receiver as claimed in claim 9 , wherein the first down-converter is configured to down-convert the sampling rate of the intermediate digital signal by use of the timing error information.

11. The single channel receiver as claimed in claim 9 , wherein the demodulator further includes a second down-converter configured to further down-convert the down-converted sampling rate of the intermediate digital signal down-converted by the first down-converter and/or a delay circuit coupled between the output of the first down-converter and the decision-directed phase error detector configured to delay the output signal of the first down-converter.

12. The single channel receiver as claimed in claim 9 , wherein the demodulator further includes a hard decision detector configured to detect the bits of the digital output signal as hard decision and/or a differential decoder configured to decode the bits of the digital output signal.

13. The single channel receiver as claimed in claim 1 , wherein the oscillator is configured to generate the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal by use of the phase error information.

14. The single channel receiver as claimed in claim 1 , wherein the first output of the demodulator is provided as a second input to the decision-directed phase error detector of the timing tracking loop.

15. The single channel receiver as claimed in claim 14 , wherein the first output of the demodulator is provided as a second input to the decision-directed phase error detector of the timing tracking loop indirectly via a delay.

16. A single channel receiver comprising:
an input terminal configured to receive an analog input signal,
an RF mixer configured to down-mix the analog input signal to an intermediate frequency by use of a phase- and/or frequency-corrected oscillator frequency signal and to shift complex-valued information contained in the analog input signal only to an imaginary part to obtain an intermediate real-valued analog signal,
an analog-to-digital-converter configured to convert the intermediate real-valued analog signal into an intermediate digital signal,
a demodulator configured to demodulate the intermediate digital signal into a digital output signal,
a phase tracking loop configured to detect zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, wherein the phase tracking loop includes a zero-crossing detector configured to detect a timing of zero-crossings between two consecutive symbols of the intermediate digital signal,
a timing tracking loop configured to detect signal shape distortions in the digital output signal to obtain timing error information representing a sample timing error in the digital output signal, and
an oscillator configured to generate the phase- and/or frequency-corrected oscillator frequency signal by use of the phase error information,
wherein the timing tracking loop includes a decision-directed phase error detector configured to compare amplitudes of the digital output signal at predetermined timings between two cons

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Goto Yuken
• Fritz Martin

Classifications

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L27/0014

  Carrier regulation (of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657) · CPC title

• H04L2027/0055

  single phase · CPC title

• H04L27/2014

  in which the phase changes in a piecewise linear manner during each symbol period, e.g. minimum shift keying, fast frequency shift keying (H04L27/201 takes precedence) · CPC title

• H04L27/106 Primary

  M-ary FSK · CPC title