Field effect transistor structure with abrupt source/drain junctions

Patent metadata

Field	Value
Publication number	US-9640634-B2
Application number	US-70063710-A
Country	US
Kind code	B2
Filing date	Feb 4, 2010
Priority date	Nov 12, 1998
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

First claim

What is claimed is:

1. A transistor, comprising:
a gate stack disposed on a substrate, the gate stack comprising a gate electrode disposed above a gate dielectric layer;
a pair of recesses disposed in the substrate, and partially underneath the gate electrode; and
a p-type doped single crystalline silicon germanium material layer disposed in the pair of recesses and partially underneath the gate electrode.

2. The transistor of claim 1 , wherein the gate electrode is a metal gate electrode.

3. The transistor of claim 1 , wherein the gate stack further comprises a pair of sidewall spacers adjacent the gate electrode and the gate dielectric layer.

4. The transistor of claim 1 , wherein the substrate has a top surface and the p-type doped single crystalline silicon germanium material layer has a top surface, and wherein the top surface of the p-type doped single crystalline silicon germanium material layer is above the top surface of the substrate.

5. The transistor of claim 4 , wherein the gate stack further comprises a pair of sidewall spacers adjacent the gate electrode and the gate dielectric layer, and wherein the p-type doped single crystalline silicon germanium material layer is adjacent to the pair of sidewall spacers.

6. The transistor of claim 1 , further comprising:
crystalline material of n type conductivity type disposed on the type doped single crystalline silicon germanium material layer disposed in the pair of recesses.

7. The transistor of claim 6 , wherein the crystalline material of n type conductivity type is selected from the group consisting of n-type silicon, and n-type silicon germanium.

8. A transistor, comprising:
a gate stack disposed on a substrate, the gate stack comprising a gate electrode disposed above a gate dielectric layer;
a pair of recesses disposed in the substrate, and partially underneath the gate electrode;
a doped silicon germanium single crystalline material layer disposed in the pair of recesses and partially underneath the gate electrode, the doped silicon germanium single crystalline material layer of at least a first conductivity type; and
a crystalline material of a second conductivity type disposed on the doped silicon germanium single crystalline material layer disposed in the pair of recesses, the second conductivity type opposite the first conductivity type.

9. The transistor of claim 8 , wherein the doped silicon germanium single crystalline material layer of the first conductivity type is selected from the group consisting of p-type silicon germanium and n-type silicon germanium.

10. The transistor of claim 8 , wherein the gate electrode is a metal gate electrode.

11. The transistor of claim 8 , wherein the gate stack further comprises a pair of sidewall spacers adjacent the gate electrode and the gate dielectric layer.

12. The transistor of claim 8 , wherein the substrate has a top surface and the doped silicon germanium single crystalline material layer has a top surface, and wherein the top surface of the doped silicon germanium single crystalline material is above the top surface of the substrate.

13. The transistor of claim 12 , wherein the gate stack further comprises a pair of sidewall spacers adjacent the gate electrode and the gate dielectric layer, and wherein the doped silicon germanium single crystalline material layer is adjacent to the pair of sidewall spacers.

14. The transistor of claim 8 , wherein the crystalline material of the second conductivity type is selected from the group consisting of p-type silicon, p-type silicon germanium, n-type silicon, and n-type silicon germanium.

15. A transistor, comprising:
a gate stack disposed on a substrate, the gate stack comprising a gate electrode disposed above a gate dielectric layer;
a pair of recesses disposed in the substrate, and partially underneath the gate electrode; and
a doped crystalline material disposed in the pair of recesses and partially underneath the gate electrode, the doped crystalline material of at least a first conductivity type; and
a crystalline material of a second conductivity type disposed on the doped crystalline material disposed in the pair of recesses, the second conductivity type opposite the first conductivity type.

16. The transistor of claim 15 , wherein the crystalline material of the second conductivity type is selected from the group consisting of p-type silicon, p-type silicon germanium, n-type silicon, and n-type silicon germanium.

Assignees

• Murthy Anand S
• Chau Robert S
• Morrow Patrick
• Jan Chia-Hong
• Packan Paul
• Intel Corp

Inventors

• Murthy Anand S
• Chau Robert S
• Morrow Patrick
• Jan Chia-Hong
• Packan Paul

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title