Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core

Patent metadata

Field	Value
Publication number	US-9640504-B2
Application number	US-201414224931-A
Country	US
Kind code	B2
Filing date	Mar 25, 2014
Priority date	Mar 17, 2009
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a first conductive layer;
forming a plurality of polymer pillars over the first conductive layer;
forming a second conductive layer over the polymer pillars to form a plurality of conductive z-interconnect structures; and
disposing a semiconductor die between the conductive z-interconnect structures and contacting the first conductive layer.

2. The method of claim 1 , further including forming a first interconnect structure over the conductive z-interconnect structures.

3. The method of claim 2 , further including forming a second interconnect structure over the conductive z-interconnect structures opposite the first interconnect structure.

4. The method of claim 1 , further including:
depositing an encapsulant around the conductive z-interconnect structures; and
forming a build-up interconnect layer over a surface of the encapsulant and electrically connected to the conductive z-interconnect structures.

5. The method of claim 4 , further including forming an integrated passive device in the build-up interconnect layer.

6. The method of claim 5 , further including configuring the integrated passive device to operate as a capacitor, resistor, or inductor.

7. A method of making a semiconductor device, comprising:
providing a conductive layer;
forming a first conductive z-interconnect structure and second conductive z-interconnect structure each in contact with the conductive layer and including an inner polymer core within the first conductive z-interconnect structure and second conductive z-interconnect structure; and
disposing a semiconductor die between the first conductive z-interconnect structure and second conductive z-interconnect structure and contacting the conductive layer.

8. The method of claim 7 , further including forming the inner polymer core in a prolate spheroid shape.

9. The method of claim 7 , further including:
depositing an encapsulant around the first conductive z-interconnect structure and second conductive z-interconnect structure; and
forming a build-up interconnect layer over a surface of the encapsulant and electrically connected to the first conductive z-interconnect structure and second conductive z-interconnect structure.

10. The method of claim 9 , further including forming an integrated passive device in the build-up interconnect layer.

11. The method of claim 10 , further including configuring the integrated passive device to operate as a capacitor, resistor, or inductor.

12. A semiconductor device, comprising:
a conductive layer;
a plurality of conductive z-interconnect structures including an inner polymer core formed over the conductive layer; and
a semiconductor die disposed between the conductive z-interconnect structures and contacting the conductive layer.

13. The semiconductor device of claim 12 , wherein the inner polymer core includes a prolate spheroid shape.

14. The semiconductor device of claim 12 , further including:
an encapsulant deposited around the conductive z-interconnect structures; and
a build-up interconnect layer formed over a surface of the encapsulant and electrically connected to the conductive z-interconnect structures.

15. The semiconductor device of claim 14 , further including an integrated passive device formed in the build-up interconnect layer.

16. The semiconductor device of claim 15 , wherein the integrated passive device is configured to operate as a capacitor, resistor or inductor.

17. A semiconductor device, comprising:
a conductive layer;
a first conductive z-interconnect structure including a first inner polymer core formed in contact with the conductive layer;
a second conductive z-interconnect structure including a second inner polymer core formed in contact with the conductive layer; and
a semiconductor die disposed between the first conductive z-interconnect structure and second conductive z-interconnect structure and contacting the conductive layer.

18. The semiconductor device of claim 17 , wherein the first inner polymer core includes a prolate spheroid shape.

19. The semiconductor device of claim 17 , further including:
an encapsulant deposited around the first conductive z-interconnect structure and second conductive z-interconnect structure; and
a build-up interconnect layer formed over a surface of the encapsulant and electrically connected to the first conductive z-interconnect structure and second conductive z-interconnect structure.

20. The semiconductor device of claim 19 , further including an integrated passive device formed in the build-up interconnect layer.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Pagaila Reza A
• Do Byung Tai
• Huang Shuangwu

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/9413

  on encapsulations · CPC title