Package substrate, semiconductor package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9640503-B2
Application number	US-201514837245-A
Country	US
Kind code	B2
Filing date	Aug 27, 2015
Priority date	Nov 27, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

First claim

What is claimed is:

1. A package substrate, comprising:
an insulating layer having opposing first and second surfaces;
a first wiring layer embedded in the insulating layer, exposed from the first surface, and having a plurality of first conductive pads;
a second wiring layer embedded in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads;
a third wiring layer formed on the first surface and electrically connected with the first wiring layer;
a plurality of first metal bumps formed on the first conductive pads correspondingly; and
at least one conductive via embedded in the insulating layer and electrically connected with the second wiring layer and the third wiring layer.

2. The package substrate of claim 1 , wherein each of the first metal bumps has an area projected onto the first surface that is less than an area of a corresponding one of the first conductive pads.

3. The package substrate of claim 1 , wherein the first wiring layer has an exposed surface lower than the first surface.

4. The package substrate of claim 1 , wherein the second wiring layer has an exposed surface lower than the second surface.

5. The package substrate of claim 1 , wherein the at least one conductive via extends to the first surface, and is coplanar with the first surface.

6. The package substrate of claim 1 , further comprising a plurality of second metal bumps formed on the second conductive pads correspondingly.

7. The package substrate of claim 6 , wherein each of the second metal bumps has an area projected onto the second surface that is less than an area of a corresponding one of the second conductive pads.

8. A semiconductor package, comprising:
the package substrate of claim 1 ;
at least one semiconductor component mounted on the package substrate in a flip chip manner; and
an encapsulant formed on the package substrate and encapsulating the semiconductor components.

9. The semiconductor package of claim 8 , wherein the semiconductor component is mounted on the first surface of the package substrate in the flip-chip manner.

10. The semiconductor package of claim 9 , wherein the semiconductor component has a solder material that encapsulates the first metal bumps.

11. The semiconductor package of claim 8 , wherein the semiconductor component is mounted on the second surface of the package substrate in the flip-chip manner.

12. The semiconductor package of claim 11 , wherein the package substrate further comprises a plurality of second metal bumps formed on the second conductive pads correspondingly, and the semiconductor component has a solder material that encapsulates the second metal bumps.

13. The semiconductor package of claim 12 , wherein each of the second metal bumps has an area projected onto the second surface that is less than an area of a corresponding one of the second conductive pads.

14. The semiconductor package of claim 8 , wherein each of the first metal bumps has an area projected onto the first surface that is less than an area of a corresponding one of the first conductive pads.

15. The package substrate of claim 8 , wherein the first wiring layer has an exposed surface lower than the first surface.

16. The package substrate of claim 8 , wherein the second wiring layer has an exposed surface lower than the second surface.

17. The package substrate of claim 1 , wherein the at least one conductive via extends to the first surface, and is coplanar with the first surface.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Sun Ming-Chen
• Lin Chun-Hsien
• Shen Tzu-Chieh
• Chiu Shih-Chao
• Pai Yu-Cheng

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title