Power semiconductor package having power semiconductor die in a support substrate with bar vias

Patent metadata

Field	Value
Publication number	US-9640474-B1
Application number	US-201615052520-A
Country	US
Kind code	B1
Filing date	Feb 24, 2016
Priority date	Feb 24, 2016
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A semiconductor package includes an output inductor placed over a support substrate, a power semiconductor die having a bottom surface situated on the support substrate and a top surface having an active region, where the output inductor is coupled to the active region on the top surface of the support substrate, and where the support substrate includes a plurality of bar vias. The output inductor is a packaged component having at least two leads in electrical connection with the active region of the power semiconductor die. The support substrate further includes routing conductors in electrical connection with the active region of the power semiconductor die. The power semiconductor die includes a control transistor and a sync transistor connected in a half-bridge.

First claim

The invention claimed is:

1. A power semiconductor package comprising:
an output inductor situated over a support substrate; and
a power semiconductor die having a bottom surface situated on said support substrate, and a top surface having an active region;
wherein said output inductor is coupled to said active region on said top surface of said support substrate, wherein said support substrate comprises a plurality of bar vias, and wherein said output inductor is a packaged component having at least two leads in electrical connection with said active region of said power semiconductor die.

2. The power semiconductor package of claim 1 , wherein said support substrate further comprises routing conductors in electrical connection with said active region of said power semiconductor die.

3. The semiconductor package of claim 1 wherein said power semiconductor die comprises a control transistor and a sync transistor connected in a half-bridge.

4. The semiconductor package of claim 3 wherein said output inductor has at least one lead coupled to a switched node of said half-bridge.

5. The semiconductor package of claim 3 wherein at least one of said control transistor and said sync transistor comprises a group III-V transistor.

6. The semiconductor package of claim 3 wherein at least one of said control transistor and said sync transistor comprises a group IV transistor.

7. The semiconductor package of claim 3 wherein said control transistor and said sync transistor are monolithically integrated on said power semiconductor die.

8. The semiconductor package of claim 1 wherein said power semiconductor die comprises a driver IC coupled to a control transistor and a sync transistor.

9. The semiconductor package of claim 1 wherein said support substrate and said output inductor are encapsulated in a molding compound.

10. A method of forming a power semiconductor package, said method comprising:
forming a support substrate having a plurality of bar vias;
forming a power semiconductor die on said support substrate, said power semiconductor die having a bottom surface situated on said support substrate, and a top surface having an active region; and
placing an output inductor over said support substrate;
wherein said output inductor is coupled to said active region on said top surface of said support substrate, and wherein said power semiconductor die comprises a control transistor and a sync transistor connected in a half-bridge.

11. The method of claim 10 wherein said output inductor is a packaged component having at least two leads in electrical connection with said active region of said power semiconductor die.

12. The method of claim 10 further comprising forming routing conductors in electrical connection with said active region of said power semiconductor die.

13. The method of claim 10 further comprising forming at least one photoresist layer on said support substrate.

14. The method of claim 10 further comprising molding said output inductor and said support substrate using a molding compound.

15. The method of claim 10 wherein at least one of said control transistor and said sync transistor comprises a group transistor.

16. The method of claim 10 wherein at least one of said control transistor and said sync transistor comprises a group IV transistor.

17. The method of claim 10 wherein said control transistor and said sync transistor are monolithically integrated on said power semiconductor die.

18. The method of claim 10 wherein said power semiconductor die comprises a driver IC coupled to said control transistor and said sync transistor.

19. A power semiconductor package comprising:
an output inductor situated over a support substrate; and
a power semiconductor die having a bottom surface situated on said support substrate, and a top surface having an active region;
wherein said output inductor is coupled to said active region on said top surface of said support substrate, wherein said support substrate comprises a plurality of bar vias, and wherein said power semiconductor die comprises a control transistor and a sync transistor connected in a half-bridge.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San
• Clavette Danny

Classifications

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/095

  of vias therein · CPC title