Wafer bonding structures and wafer processing methods

Patent metadata

Field	Value
Publication number	US-9640451-B2
Application number	US-201514597569-A
Country	US
Kind code	B2
Filing date	Jan 15, 2015
Priority date	Jun 30, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer.

First claim

What is claimed is:

1. A wafer processing method, comprising:
providing a to-be-processed wafer having a first surface with a plurality of device regions and dicing groove regions between adjacent device regions, and a second surface corresponding to the first surface;
providing a capping wafer having a first surface of the capping wafer and a second surface of the capping wafer corresponding to the first surface of the capping wafer;
bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer such that an edge of the capping wafer coincides with an edge of the to-be-processed wafer;
performing an edge trimming process onto the to-be-processed wafer such that a radius of the to-be-processed wafer is smaller than a radius of the capping wafer and such that the capping wafer provides an umbrella function with respect to the to-be-processed wafer;
grinding the second surface of the capping wafer to reduce a thickness of the capping wafer, thereby providing a thinned capping layer on the trimmed to-be-processed wafer; and
etching the thinned capping wafer, thereby exposing the first surface of the trimmed to-be-processed wafer of the dicing groove regions.

2. The method according to claim 1 , wherein:
a plurality of device layers are formed on the device regions of the first surface of the to-be-processed wafer;
dicing grooves are formed between adjacent device layers and in the dicing groove regions; and
the plurality of device layers are bonded with the first surface of the capping wafer.

3. The method according to claim 2 , wherein the device layers further include:
device structures formed in the device regions of the first surface of the to-be-processed wafer;
a dielectric layer formed on the first surface of the to-be-processed wafer to cover the device structures; and
electrical interconnect structures formed within the dielectric layer and having a top surface exposed by the dielectric layer.

4. The method according to claim 3 , wherein bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer further includes:
pressing the first surface of the to-be-processed wafer on the first surface of the to-be-processed wafer onto the first surface of the capping wafer; and
performing a thermal annealing process to cause a top surface of the electrical interconnect structure to fuse with the first surface of the capping wafer.

5. The method according to claim 4 , wherein:
the first surface of the capping wafer has a plurality of conductive layers corresponding to the top surface of the electrical interconnect structures; and
the conductive layers are fused with the electrical interconnect structures in the dielectric layer of the first surface of the to-be-processed wafer.

6. The method according to claim 4 , wherein:
an insulation layer is formed on the first surface of the capping wafer; and
the insulation layer is fused with the dielectric layer of the first surface of the to-be-processed wafer.

7. The method according to claim 1 , further including:
cleaning the second surface of the thinned capping layer, prior to etching the thinned capping wafer, wherein:
the second surface of the capping wafer is cleaned by a wet cleaning process; and
a cleaning solution of the wet cleaning process is de-ionized water.

8. The method according to claim 7 , wherein:
the cleaning solution is sprayed toward the second surface of the capping wafer; and
a spray direction of the cleaning solution has a pre-determined angle with the second surface of the capping wafer.

9. The method according to claim 7 , after cleaning the second surface of the capping wafer and before etching the capping wafer, further including:
performing a speed ring dry process.

10. The method according to claim 1 , wherein:
the radius of the to-be-processed wafer is reduced in a range of approximately 3 mm˜5 mm.

11. The method according to claim 1 , wherein:
the edge trimming process uses a knife feeding from an edge of the to-be-processed wafer to a center of the to-be-processed wafer to reduce the radius of the to-be-processed wafer.

12. The method according to claim 11 , wherein:
a rotation speed of the knife is in a range of approximately 2000 rpm˜3000 rpm; and
a feeding depth of the knife is in a range of approximately 400 μm˜750 μm.

13. The method according to claim 1 , wherein:
a thickness of the grinded capping wafer is in a range of approximately 3 μm˜400 μm.

14. The method according to claim 1 , wherein etching the capping wafer further includes:
forming a mask layer exposing a portion of the grinded capping wafer corresponding to the dicing groove regions of the to-be-processed wafer on the second surface of the to-be-processed wafer; and
etching the grinded capping wafer using the mask layer as an etching mask until the dicing groove regions of the to-be-processed wafer are exposed.

15. The method according to claim 14 , wherein:
a plurality of the testing pads are formed in the dicing groove regions of the to-be-processed wafer; and
a performance of the device regions of the to-be-processed wafer is tested through the testing pads after etching the grinded capping wafer to expose the dicing groove regions of the first surface of the to-be-processed wafer.

16. The method according to claim 1 , wherein:
after the edge trimming process, the to-be-processed wafer has a trimmed edge perpendicular to the first surface of the to-be-processed wafer.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zheng Chao
• Wang Wei
• Ma Junde

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title