Methods of forming semiconductor elements using micro-abrasive particle stream

Patent metadata

Field	Value
Publication number	US-9640437-B2
Application number	US-84261210-A
Country	US
Kind code	B2
Filing date	Jul 23, 2010
Priority date	Jul 23, 2010
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

First claim

The invention claimed is:

1. A method of fabricating a microelectronic unit, comprising:
providing a semiconductor element having a front surface facing in a first direction and a rear surface remote from the front surface, a plurality of active semiconductor devices therein, and a plurality of conductive pads exposed at the front surface, the conductive pads having top surfaces exposed at the front surface of the semiconductor element and bottom surfaces opposite the top surfaces;
forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface;
forming at least one second opening extending from the at least one first opening to the bottom surface of at least one of the conductive pads, the at least one second opening exposing at least a portion of the bottom surface of the at least one conductive pad;
forming at least one conductive via extending within the at least one second opening and coupled to the bottom surface of a respective one of the conductive pads;
forming a dielectric region filling the at least one first opening, the dielectric region having a top surface facing in a second direction opposite from the first direction, and forming an aperture penetrating through the dielectric region; and
forming at least one conductive contact and at least one conductive interconnect coupled thereto, wherein the step of forming the at least one conductive interconnect includes depositing an electrically conductive material in contact with the bottom surface of the at least one conductive pad, each conductive interconnect extending within one or more of the first openings at least within the aperture and coupled to the at least one conductive pad, the at least one conductive contact exposed at the rear surface of the semiconductor element for electrical connection to an external device, and wherein the step of forming the at least one conductive contact includes depositing an electrically conductive material such that a bottom surface of the conductive contact facing in the first direction is formed in direct contact with the top surface of the dielectric region, the at least one conductive contact located completely within a boundary defined by edges of the first opening in a lateral direction along the rear surface, the bottom surface of the conductive contact located at or above a plane defined by the rear surface of the semiconductor element,
wherein the step of forming the at least one conductive interconnect is performed after forming the conductive via, such that the conductive interconnect is coupled to the respective one of the conductive pads through the at least one conductive via, and
wherein the step of forming the at least one second opening includes, from within the second opening, removing at least a portion of a passivation layer contacting the bottom surface of the respective one of the conductive pads.

2. A method as claimed in claim 1 , wherein at least one of the plurality of conductive pads are electrically connected to at least one of the plurality of active semiconductor devices.

3. A method as claimed in claim 1 , wherein the at least one conductive contact overlies the rear surface of the semiconductor element.

4. A method as claimed in claim 1 , wherein the first opening has a first width in a lateral direction along the rear surface, and at least one of the conductive contacts has a second width in the lateral direction, the first width being greater than the second width.

5. A method as claimed in claim 1 , wherein the step of forming the first opening includes forming a channel shape.

6. A method as claimed in claim 1 , further comprising, after forming the first opening, reducing the surface roughness of an inner surface of the first opening.

7. A method as claimed in claim 6 , wherein the step of reducing the surface roughness of the inner surface of the first opening includes using wet etching or plasma etching.

8. A method as claimed in claim 1 , wherein the conductive interconnect has a cylindrical or frusto-conical shape.

9. A method as claimed in claim 1 , wherein the conductive interconnect includes an internal space, further comprising the step of filling the internal space with a dielectric material.

10. A method as claimed in claim 1 , wherein the step of forming the at least one second opening includes forming at least two second openings extending from one of the first openings and at least partially exposing the bottom surfaces of respective ones of the conductive pads.

11. A method as claimed in claim 1 , wherein the step of forming the at least one conductive interconnect forms two or more conductive interconnects at least within the first opening extending to two or more respective ones of the at least one conductive vias.

12. A method as claimed in claim 1 , wherein the step of forming the conductive interconnect includes plating an inner surface of the aperture.

13. A method as claimed in claim 1 , wherein the dielectric region is deposited by electrochemical polymer deposition.

14. A method as claimed in claim 13 , wherein the step of forming the dielectric region includes coating a surface having a negative angle with respect to the rear surface.

15. A method as claimed in claim 1 , wherein the step of forming the dielectric region includes coating a surface having a negative angle with respect to the rear surface.

16. A method as claimed in claim 1 , wherein the aperture has a contour not conforming to a contour of the at least one of the first or second openings.

17. A method as claimed in claim 16 , wherein the aperture has a contour not conforming to a contour of the first opening.

18. A method as claimed in claim 16 , wherein the aperture has a contour not conforming to a contour of the second opening.

19. A method as claimed in claim 1 , wherein each conductive contact has a width in the lateral direction that is greater than a width of at least a portion of the conductive interconnect that is adjacent the conductive contact.

20. A method as claimed in claim 1 , wherein the at least one first opening is formed by directing a jet of abrasive particles towards the semiconductor element.

21. A method as claimed in claim 20 , wherein an average size of the abrasive particles is at least 1 micrometer.

22. A method as claimed in claim 20 , wherein the jet of abrasive particles includes a gas medium.

23. A method as claimed in claim 20 , wherein the jet of abrasive particles includes a liquid medium.

24. A method of fabricating an interconnection substrate, comprising:
providing a semiconductor element having a front surface facing in a first direction and a rear surface remote from the front surface, and at least one conductive element having a top surface exposed at the front surface;
forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface;
forming at least one second opening extending from the at least one first opening and exposing at least a portion of the at least one conductive element, the second opening not extending through the at least one conductive element;
forming a dielectric region filling the at least one first opening, the dielectric region having a top surface facing in a second direction opposite from the first direction, and forming an aperture penetrating through the dielectric region; and
forming at least one conduc

Assignees

• Oganesian Vage
• Haba Belgacem
• Mitchell Craig
• Mohammed Ilyas
• Savalia Piyush
• Tessera Inc

Inventors

• Oganesian Vage
• Haba Belgacem
• Mitchell Craig
• Mohammed Ilyas
• Savalia Piyush

Classifications

• H10W72/9226

  with via interconnections · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title