Self-limited planarization of hardmask

Patent metadata

Field	Value
Publication number	US-9640409-B1
Application number	US-201615013400-A
Country	US
Kind code	B1
Filing date	Feb 2, 2016
Priority date	Feb 2, 2016
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A method for processing a semiconductor substrate includes a) providing a substrate stack including a first layer, a plurality of cores arranged in a spaced relationship on the first layer and one or more underlying layers arranged below the first layer; b) depositing a conformal layer on the first layer and the plurality of cores; c) partially etching the conformal layer to create spacers arranged adjacent to sidewalls of the plurality of cores, wherein the partial etching of the conformal layer causes upper portions of the spacers to have an asymmetric profile; d) selectively etching the plurality of cores relative to the spacers and the first layer; e) depositing polymer film on sidewalls of the spacers; and f) etching the upper portions of the spacers to remove the asymmetric profile and to planarize the upper portions of the spacers.

First claim

What is claimed is:

1. A method for processing a semiconductor substrate, comprising:
a) providing a substrate stack including a first layer, a plurality of cores arranged in a spaced relationship on the first layer and one or more underlying layers arranged below the first layer;
b) depositing a conformal layer on the first layer and the plurality of cores;
c) partially etching the conformal layer to create spacers arranged adjacent to sidewalls of the plurality of cores, wherein the partial etching of the conformal layer causes upper portions of the spacers to have an asymmetric profile;
d) selectively etching the plurality of cores relative to the spacers and the first layer;
e) depositing polymer film on sidewalls of the spacers; and
f) etching the upper portions of the spacers to remove the asymmetric profile and to planarize the upper portions of the spacers.

2. The method of claim 1 , further comprising g) etching the polymer film.

3. The method of claim 2 , further comprising repeating b) to g) one or more times.

4. The method of claim 1 , wherein f) is performed in a substrate processing chamber including a substrate support, an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper chamber region and the lower chamber region.

5. The method of claim 4 , wherein the gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region.

6. The method of claim 5 , further comprising:
controlling pressure in the substrate processing chamber during f) in a range from 0.4 Torr to 10 Torr; and
supplying an etch gas mixture including fluorine-based gas to the upper chamber region.

7. The method of claim 4 , further comprising supplying power to the inductive coil in a range from 200 W to 3 kW during f).

8. The method of claim 4 , further comprising supplying RF bias power to the substrate support in a range from 50 W to 1000 W during f).

9. The method of claim 6 , wherein the etch gas mixture a gas selected form a group consisting of sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), carbon tetrafluoride (CFO, difluoromethane (CH 2 F 2 ), fluoromethane (CH 3 F), hexafluoro-2-butyne (C 4 F 6 ), and octafluorocyclobutane (C 4 F 8 ).

10. The method of claim 9 , wherein the etch gas mixture further includes one or more gases selected from a group consisting of argon (Ar) and helium (He).

11. The method of claim 1 , wherein the depositing the conformal layer in b) includes atomic layer deposition.

12. The method of claim 1 , wherein the partial etching in c) is performed in an inductively coupled plasma (ICP) chamber.

13. The method of claim 1 , wherein the plurality of cores includes amorphous silicon film.

14. The method of claim 1 , wherein the conformal layer includes a material selected form a group consisting of silicon nitride, silicon and silicon dioxide.

15. A method for processing a semiconductor substrate, comprising:
a) providing a substrate stack including a first layer, a plurality of cores arranged in a spaced relationship on the first layer and one or more underlying layers arranged below the first layer;
b) depositing a conformal layer on the first layer and the plurality of cores;
c) partially etching the conformal layer to create spacers arranged adjacent to sidewalls of the plurality of cores,
wherein the partial etching of the conformal layer causes upper portions of the spacers to have an asymmetric profile, and
wherein a polymer film remains on sidewalls of the spacers after c); and
d) etching the upper portions of the spacers to remove the asymmetric profile and to planarize the upper portions of the spacers.

16. The method of claim 15 , further comprising e) etching the polymer film and the plurality of cores.

17. The method of claim 16 , further comprising repeating b) to e) one or more times.

18. The method of claim 1 , wherein d) is performed in a substrate processing chamber including a substrate support, an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper chamber region and the lower chamber region.

19. The method of claim 18 , wherein the gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region.

20. The method of claim 19 , further comprising:
controlling pressure in the substrate processing chamber during d) in a range from 0.4 Torr to 10 Torr; and
supplying an etch gas mixture including fluorine-based gas to the upper chamber region.

21. The method of claim 18 , further comprising supplying power to the inductive coil in a range from 200 W to 3 kW during d).

22. The method of claim 18 , further comprising supplying RF bias power to the substrate support in a range from 50 W to 1000 W during d).

23. The method of claim 20 , wherein the etch gas mixture a gas selected form a group consisting of sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), carbon tetrafluoride (CFO, difluoromethane (CH 2 F 2 ), fluoromethane (CH 3 F), hexafluoro-2-butyne (C 4 F 6 ), and octafluorocyclobutane (C 4 F 8 ).

24. The method of claim 23 , wherein the etch gas mixture further includes one or more gases selected from a group consisting of argon (Ar) and helium (He).

25. The method of claim 15 , wherein the depositing the conformal layer in b) includes atomic layer deposition.

26. The method of claim 15 , wherein the partial etching in c) is performed in an inductively coupled plasma (ICP) chamber.

27. The method of claim 15 , wherein the plurality of cores includes amorphous silicon film.

28. The method of claim 15 , wherein the conformal layer includes a material selected form a group consisting of silicon nitride, silicon and silicon dioxide.

29. A self-limiting etching method for planarizing asymmetric surfaces of a substrate, comprising:
arranging a substrate on a substrate support of a substrate processing chamber,
wherein the substrate includes a feature including an upper portion with an asymmetric profile, and
wherein the substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper chamber region and the lower chamber region;
controlling pressure in the substrate processing chamber in a range from 0.4 Torr to 10 Torr;
supplying an etch gas mixture including fluorine-based gas to the upper chamber region; and
etching the upper portion of the feature to remove the asymmetric profile and to planarize the upper portion of the feature.

30. The method of claim 29 , further comprising supplying power to the inductive coil in a range from 200 W to 3 kW during the etching.

31. The method of claim 30 , further comprising supplying RF bias power to the substrate support in a range from 50 W to 1000 W during the etching.

32. The method of claim 30 , wherein the etch gas mixture a gas selected form a group consisting of sulfur hexafluoride

Assignees

• Lam Res Corp

Inventors

• Yang Dengliang
• Park Joon Hong

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10P95/066

  the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title

• H10P50/242

  of Group IV materials · CPC title