Control mechanism for fine-tuned cache to backing-store synchronization

Patent metadata

Field	Value
Publication number	US-9639466-B2
Application number	US-201213664387-A
Country	US
Kind code	B2
Filing date	Oct 30, 2012
Priority date	Oct 30, 2012
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.

First claim

We claim:

1. A method for processing commands received by an intermediary cache from one or more clients, wherein the intermediary cache is coupled to an external memory via frame buffer logic, the method comprising:
receiving a first write command from an arbiter unit, wherein the first write command specifies a first memory address;
determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address;
causing data associated with the first write command to be written into the first cache line;
marking the first cache line as dirty;
comparing a total number of cache lines marked as dirty in the set of cache lines to a first threshold value, wherein the first threshold value is adjustable from a first value to a second value that is greater than the first value, and, when the first threshold value equals the second value, fewer dirty data notifications are transmitted to the frame buffer logic when data is written to the first cache line multiple times via multiple write commands, relative to when the first threshold value equals the first value; and
comparing the total number of cache lines marked as dirty to a second threshold value that is adjustable and is greater than the first threshold value, wherein:
if the total number of cache lines marked as dirty is less than the first threshold value, then no dirty data notification is transmitted to the frame buffer logic,
if the total number of cache lines marked as dirty is greater than or equal to the first threshold value but less than or equal to the second threshold value, then only a first dirty data notification is transmitted to the frame buffer logic that specifies a least recently used dirty cache line included in the set of cache lines, wherein the frame buffer logic is configured to, in response to receiving the first dirty data notification, assign a prioritization to the first dirty data notification and then schedule the first dirty data notification for processing according to the prioritization, and
if the total number of cache lines marked as dirty is greater than the second threshold value, then both the first dirty data notification and a high-priority clean notification are transmitted to the frame buffer logic, wherein the frame buffer logic is configured to, in response to receiving the high-priority clean notification, immediately retrieve dirty data resident in one or more cache lines included in the set of cache lines,
wherein each dirty data notification indicates a particular cache line and does not include any dirty data associated with the particular cache line.

2. The method of claim 1 , wherein the frame buffer logic is configured to cause dirty data residing in the least recently used dirty cache line to be written to a corresponding entry in a dynamic random access memory serving as local memory to a graphics processing unit when the frame buffer logic processes the first dirty data notification.

3. The method of claim 1 , wherein the first dirty data notification and the high-priority clean notification are transmitted to the frame buffer logic simultaneously via a single notification.

4. The method of claim 3 , wherein the frame buffer logic is configured to process the high-priority clean notification before the dirty data notification.

5. The method of claim 1 , further comprising comparing the total number of cache lines marked as dirty to a third threshold value that is greater than the second threshold value, wherein:
if the total number of cache lines marked as dirty is greater than the second threshold value but less than the third threshold value, then both the first dirty data notification and a high-priority clean notification are transmitted to the frame buffer logic, and
if the total number of cache lines marked as dirty is equal to the third threshold value, then the first write command is stalled.

6. The method of claim 1 , wherein the first dirty data notification and the high-priority clean notification are transmitted separately as two different notifications to the frame buffer logic.

7. The method of claim 1 , wherein adjusting the first threshold causes the intermediary cache to operate as a first type of cache included in a plurality of different types of caches.

8. The method of claim 7 , wherein adjusting the first threshold value to a higher value than a current value causes the intermediary cache to operate as a write-back cache.

9. The method of claim 7 , wherein adjusting the first threshold value to a lower value than a current value causes the intermediary cache to operate as a write-through cache.

10. The method of claim 1 , wherein the first threshold is adjustable to a lesser value to allow a phased computation to be performed.

11. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to process commands received by an intermediary cache from one or more clients, wherein the intermediary cache is coupled to an external memory via frame buffer logic, by performing the steps of:
receiving a first write command from an arbiter unit, wherein the first write command specifies a first memory address;
determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address;
causing data associated with the first write command to be written into the first cache line;
marking the first cache line as dirty;
comparing a total number of cache lines marked as dirty in the set of cache lines to a first threshold value, wherein the first threshold value is adjustable from a first value to a second value that is greater than the first value, and, when the first threshold value equals the second value, fewer dirty data notifications are transmitted to the frame buffer logic when data is written to the first cache line multiple times via multiple write commands, relative to when the first threshold value equals the first value; and
comparing the total number of cache lines marked as dirty to a second threshold value that is adjustable and is greater than the first threshold value, wherein:
if the total number of cache lines marked as dirty is less than the first threshold value, then no dirty data notification is transmitted to the frame buffer logic,
if the total number of cache lines marked as dirty is greater than or equal to the first threshold value but less than or equal to the second threshold value, then only a first dirty data notification is transmitted to the frame buffer logic that specifies a least recently used dirty cache line included in the set of cache lines, wherein the frame buffer logic is configured to, in response to receiving the first dirty data notification, assign a prioritization to the first dirty data notification and then schedule the first dirty data notification for processing according to the prioritization, and
if the total number of cache lines marked as dirty is greater than the second threshold value, then both the first dirty data notification and a high-priority clean notification are transmitted to the frame buffer logic, wherein the frame buffer logic is configured to, in response to receiving the high-priority clean notification, immediately retrieve dirty data resident in one or more cache lines included in the set of cache lines,
wherein each dirty data notification indicates a particular cache line and does not include any dirty data associated with the particular cache line.

12. The non-transitory computer-readable storage medium of claim 11 , wherein the frame buffer logic is configured to cause di

Assignees

• Nvidia Corp

Inventors

• Robertson James Patrick
• Muthler Gregory Alan
• Hossain Hemayet
• Purcell Timothy John
• Mehra Karan
• Holmqvist Peter B
• Lynch George R

Classifications

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title

• G06F12/084 Primary

  with a shared cache · CPC title