Functional unit capable of executing approximations of functions

Patent metadata

Field	Value
Publication number	US-9639355-B2
Application number	US-201414216884-A
Country	US
Kind code	B2
Filing date	Mar 17, 2014
Priority date	Sep 24, 2010
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C 0+ C 1 X 2+ C 2 X 2 2 . The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C 1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X 2 term of the second instruction.

First claim

What is claimed:

1. A semiconductor chip comprising:
a decode unit to decode a first instruction, the first instruction being an instruction to approximate a function with a calculation C 0 +C 1 X 2 +C 2 X 2 2 ; and
a functional unit to perform the decoded first instruction, wherein the functional unit is to receive an operand X 1 , an operand X 2 and an operand X 2 2 , wherein the operand X 2 2 is to be calculated in a pipeline stage that is prior to an execution pipeline stage, and wherein the functional unit is to store a result of the calculation C 0 +C 1 X 2 +C 2 X 2 2 , in which C 0 , C 1 , and C 2 are coefficients that the semiconductor chip is to determine from the operand X 1 .

2. A semiconductor chip comprising:
a decode unit to decode a first instruction, the first instruction being an instruction to approximate a function with a calculation C 0 +C 1 X 2 +C 2 X 2 2 ; and
a functional unit to perform the decoded first instruction, wherein the functional unit is to receive an operand X 1 , an operand X 2 and an operand X 2 2 , wherein the operand X 2 2 is to be calculated in a stage that is prior to an execution stage, and wherein the functional unit is to store a result of the calculation C 0 +C 1 X 2 +C 2 X 2 2 , in which C 0 , C 1 , and C 2 are coefficients that the semiconductor chip is to determine from the operand X 1 , and wherein the operand X 2 2 is to be calculated in said stage that is to be prior to a stage at which the C 0 , the C 1 , and the C 2 coefficients are to be determined.

3. The semiconductor chip of claim 1 , wherein the operand X 2 2 is to be calculated in a scheduler.

4. The semiconductor chip of claim 1 , wherein the functional unit has a look up table to determine the coefficients C 0 , C 1 , and C 2 from the operand X 1 .

5. The semiconductor chip of claim 1 , wherein the first instruction is a reciprocal function approximation instruction.

6. The semiconductor chip of claim 1 , wherein the first instruction is for a calculation 1/(X 1/2 ).

7. The semiconductor chip of claim 1 , wherein the first instruction is for a calculation log 2 (X).

8. The semiconductor chip of claim 1 , wherein the decode unit is also to decode a floating point multiply instruction, and the functional unit is also to perform the decoded floating point multiply instruction.

9. The semiconductor chip of claim 1 , wherein the functional unit includes a multiplier that includes divided Wallace tree circuitry that is divided into two portions.

10. The semiconductor chip of claim 1 , wherein the decode unit is also to decode a floating point multiply instruction, and the functional unit is also to perform the decoded floating point multiply instruction, and wherein the functional unit includes a multiplier that includes divided Wallace tree circuitry that is divided into two portions.

11. A computer system, comprising:
a memory;
a graphics processor coupled with the memory; and
a processor coupled with the memory, the processor comprising:
a decode unit to decode a first instruction, the first instruction being an instruction to approximate a function according to C 0 +C 1 X 2 +C 2 X 2 2 ; and
a functional unit to perform the decoded first instruction, wherein the functional unit is to receive an operand X 1 , an operand X 2 and an operand X 2 2 , wherein the operand X 2 2 is to be calculated in a scheduler pipeline stage that is prior to an execution pipeline stage, and wherein the functional unit is to store a result of C 0 +C 1 X 2 +C 2 X 2 2 , in which C 0 , C 1 , and C 2 are coefficients that the semiconductor chip is to determine from the operand X 1 .

12. The computer system of claim 11 , wherein the operand X 2 2 is to be calculated in said scheduler pipeline stage that is to be prior to a pipeline stage at which the C 0 , the C 1 , and the C 2 coefficients are to be determined.

13. The computer system of claim 11 , wherein the operand X 2 2 is to be calculated in a scheduler.

14. The computer system of claim 11 , wherein the functional unit has a look up table to determine the coefficients C 0 , C 1 , and C 2 from the operand X 1 .

15. The computer system of claim 11 , wherein the first instruction is a reciprocal function approximation instruction.

16. The computer system of claim 11 , wherein the first instruction is for a calculation 1(X 1/2 ).

17. The computer system of claim 11 , wherein the first instruction is for a calculation log 2 (X).

18. A semiconductor chip comprising:
a decode unit to decode a first instruction, the first instruction being an instruction to approximate a function as C 0 +C 1 X 2 +C 2 X 2 2 ; and
a functional unit to perform the decoded first instruction, wherein the functional unit is to receive an operand X 1 , an operand X 2 and an operand X 2 2 , and wherein the functional unit is to store a result of said C 0 +C 1 X 2 +C 2 X 2 2 , in which C 0 , C 1 , and C 2 are coefficients that the functional unit is to determine from the operand X 1 , wherein the operand X 2 2 is to be calculated before the operand X 1 is delivered to the functional unit, and wherein the operand X 2 2 is to be calculated before the operand X 1 is to be used to determine the C 0 , the C 1 , and the C 2 coefficients.

19. The semiconductor chip of claim 18 , wherein the decode unit is also to decode a floating point multiply instruction, and the functional unit is also to perform the decoded floating point multiply instruction.

20. The semiconductor chip of claim 18 , wherein the functional unit includes a multiplier that includes divided Wallace tree circuitry that is divided into two portions.

21. The semiconductor chip of claim 18 , wherein the decode unit is also to decode a floating point multiply instruction, and the functional unit is also to perform the decoded floating point multiply instruction, and wherein the functional unit includes a multiplier that includes divided Wallace tree circuitry that is divided into two portions.

Assignees

• Intel Corp

Inventors

• Pineiro Alex
• Fletcher Thomas D
• Hickmann Brian J

Classifications

• G06F2101/12

  Reciprocal functions · CPC title

• G06F9/3895

  for complex operations, e.g. multidimensional or interleaved address generators, macros · CPC title

• G06F2101/08

  Powers or roots · CPC title

• G06F1/035

  Reduction of table size {(G06F1/0314 takes precedence)} · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title