Solar cell emitter region fabrication with differentiated P-type and N-type region architectures

Patent metadata

Field	Value
Publication number	US-9634177-B2
Application number	US-201514919049-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Dec 20, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

First claim

What is claimed is:

1. A method of fabricating a back contact solar cell, the method comprising:
providing a substrate having a light-receiving surface and a back surface;
forming a first thin dielectric layer on the back surface of the substrate;
forming a first polycrystalline silicon emitter region of a first conductivity type on the first thin dielectric layer;
forming a recess in the back surface of the substrate;
forming a second thin dielectric layer in the recess;
forming a second polycrystalline silicon emitter region of a second, different, conductivity type on the second thin dielectric layer in the recess;
forming a third thin dielectric layer laterally directly between the first and second polycrystalline silicon emitter regions;
forming a first conductive contact structure on the first polycrystalline silicon emitter region; and
forming a second conductive contact structure on the second polycrystalline silicon emitter region, wherein the first polycrystalline silicon emitter region overlaps the second polycrystalline silicon emitter region.

2. The method of claim 1 , further comprising:
forming an insulator layer on the first polycrystalline silicon emitter region, wherein the first conductive contact structure is disposed through the insulator layer, and wherein a portion of the second polycrystalline silicon emitter region overlaps the insulator layer but is separate from the first conductive contact structure.

3. The method of claim 1 , further comprising:
forming an insulator layer on the first polycrystalline silicon emitter region; and
forming the polycrystalline silicon layer of the second conductivity type on the insulator layer, wherein the first conductive contact structure is disposed through the polycrystalline silicon layer of the second conductivity type and through the insulator layer.

4. The method of claim 1 , wherein forming the recess comprises forming a recess having a texturized surface.

5. The method of claim 1 , wherein forming the first polycrystalline silicon emitter region and forming the first thin dielectric layer comprises forming on a flat portion of the back surface of the substrate, and wherein forming the second polycrystalline silicon emitter region and the second thin dielectric layer comprises forming on a texturized portion of the back surface of the substrate.

6. The method of claim 1 , wherein forming the first and second conductive contact structures comprises forming an aluminum-based metal seed layer on the first and second polycrystalline silicon emitter regions, respectively, and forming a metal layer on the aluminum-based metal seed layer.

7. The method of claim 1 , wherein forming the first and second conductive contact structures comprises forming a metal silicide layer on the first and second polycrystalline silicon emitter regions, respectively, and forming a metal layer on the metal silicide layer.

8. The method of claim 7 , wherein forming the metal silicide layer comprises forming a material selected from the group consisting of titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), tungsten silicide (WSi 2 ), and nickel silicide (NiSi or NiSi 2 ).

9. The method of claim 1 , further comprising:
forming a fourth thin dielectric layer on the light-receiving surface of the substrate;
forming a polycrystalline silicon layer of the second conductivity type on the fourth thin dielectric layer; and
forming an anti-reflective coating (ARC) layer on the polycrystalline silicon layer of the second conductivity type.

10. The method of claim 1 , wherein providing the substrate comprises providing an N-type monocrystalline silicon substrate, and wherein the first conductivity type is P-type and the second conductivity type is N-type.

11. The method of claim 1 , wherein providing the substrate comprises providing a P-type monocrystalline silicon substrate, and wherein the first conductivity type is N-type and the second conductivity type is P-type.

Assignees

• Rim Seung Bum
• Smith David D
• Qiu Taiqing
• Westerberg Staffan
• Tracy Kieran Mark
• Balu Venkatasubramani
• Sunpower Corp

Inventors

• Rim Seung Bum
• Smith David D
• Qiu Taiqing
• Westerberg Staffan
• Tracy Kieran Mark
• Balu Venkatasubramani

Classifications

• Y02E10/547

  Monocrystalline silicon PV cells · CPC title

• Y02E10/50

  Photovoltaic [PV] energy · CPC title

• H10F71/103

  including only Group IV materials · CPC title

• H10F71/10

  the devices comprising amorphous semiconductor material · CPC title

• H10F71/1221

  comprising polycrystalline silicon · CPC title