Method for producing photoelectric conversion element

US9257593B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9257593-B2
Application numberUS-201314029367-A
CountryUS
Kind codeB2
Filing dateSep 17, 2013
Priority dateMar 25, 2011
Publication dateFeb 9, 2016
Grant dateFeb 9, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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There is provided a method of producing a photovoltaic element comprising: a first step in which an i-type amorphous silicon layer ( 16 ) and an n-type amorphous silicon layer ( 14 ) are formed over a light-receiving surface of an n-type monocrystalline silicon substrate ( 18 ); a second step in which an i-type amorphous silicon layer ( 22 a ) and an n-type amorphous silicon layer ( 23 a ) are formed over a back surface of the n-type monocrystalline silicon substrate ( 18 ); and a third step in which, after the first step and the second step are completed, protection layers are formed over the n-type amorphous silicon layer ( 14 ) and the n-type amorphous silicon layer ( 23 a ).

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of producing a photovoltaic element, comprising: a first step in which a first amorphous semiconductor-based layer is formed over a light-receiving surface of a crystalline semiconductor-based substrate; a second step in which a second amorphous semiconductor-based layer is formed over a back surface of the crystalline semiconductor-based substrate; and a third step in which, after the first step and the second step are completed, a first protection layer is formed over the first amorphous semiconductor-based layer after a second protection layer is formed over the second amorphous semiconductor-based layer, wherein the first protection layer is directly in contact with the first amorphous semiconductor-based layer; wherein the second amorphous semiconductor-based layer includes an n-type semiconductor layer provided in a first region and a p-type semiconductor layer provided in a second region different from the first region, and the photovoltaic element includes a first electrode provided on the n-type semiconductor layer and a second electrode provided on the p-type semiconductor layer. 2. The method of producing the photovoltaic element according to claim 1 , wherein the crystalline semiconductor-based substrate is of an n-type, the first amorphous semiconductor-based layer comprises: a first i-type amorphous semiconductor-based layer formed over the light-receiving surface of the crystalline semiconductor-based substrate; and a first n-type amorphous semiconductor-based layer formed over the first i-type amorphous semiconductor-based layer, and the second amorphous semiconductor-based layer comprises: a second i-type amorphous semiconductor-based layer formed over the back surface of the crystalline semiconductor-based substrate; and a second n-type amorphous semiconductor-based layer formed over the second i-type amorphous semiconductor-based layer. 3. The method of producing the photovoltaic element according to claim 1 , wherein either one or both of the first protection layer and the second protection layer comprises at least one of the group of aluminum oxide, aluminum nitride, silicon nitride, and silicon oxide. 4. The method of producing the photovoltaic element according to claim 2 , wherein either one or both of the first protection layer and the second protection layer comprises at least one of the group of aluminum oxide, aluminum nitride, silicon nitride, and silicon oxide.

Assignees

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Classifications

  • H10F77/311Primary

    for photovoltaic cells · CPC title

  • Arrangements for electrodes of back-contact photovoltaic cells · CPC title

  • Shapes of potential barriers · CPC title

  • including only Group IV materials · CPC title

  • the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells · CPC title

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What does patent US9257593B2 cover?
There is provided a method of producing a photovoltaic element comprising: a first step in which an i-type amorphous silicon layer ( 16 ) and an n-type amorphous silicon layer ( 14 ) are formed over a light-receiving surface of an n-type monocrystalline silicon substrate ( 18 ); a second step in which an i-type amorphous silicon layer ( 22 a ) and an n-type amorphous silicon layer ( 23 a ) …
Who is the assignee on this patent?
Sanyo Electric Co, Panasonic Ip Man Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10F77/311. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).