Embedded transistor

Patent metadata

Field	Value
Publication number	US-9634134-B2
Application number	US-201414465578-A
Country	US
Kind code	B2
Filing date	Aug 21, 2014
Priority date	Oct 13, 2011
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate having a first set of trenches and a second set of trenches;
depositing a dielectric material in both the first set of trenches and the second set of trenches;
removing the dielectric material in the second set of trenches;
implanting a dielectric growth modifier into a first sidewall of a first one of the second set of trenches; and
forming a gate insulator layer along the first sidewall and a bottom of the first one of the second set of trenches, wherein the gate insulator layer forms at a different rate along the first sidewall than along the bottom such that the gate insulator layer has a decreasing thickness along the first sidewall.

2. The method of claim 1 , wherein the dielectric growth modifier comprises fluorine.

3. The method of claim 1 , further comprising implanting the dielectric growth modifier into a second sidewall of the first one of the second set of trenches different from the first sidewall.

4. The method of claim 3 , wherein the implanting the dielectric growth modifier into the first sidewall is performed at a first angle that is greater than zero.

5. The method of claim 4 , wherein the first angle is greater than an arctangent of a width of the trench divided by a height of the trench.

6. The method of claim 4 , wherein the implanting the dielectric growth modifier into the second sidewall is performed at a second angle that is opposite the first angle.

7. The method of claim 1 , wherein the first one of the second set of trenches trench has a second sidewall that remains free from the dielectric growth modifier.

8. The method of claim 1 , wherein the implanting the dielectric growth modifier into the first sidewall is performed while the substrate is being rotated.

9. The method of claim 1 , wherein the gate insulator layer has a difference between a first thickness at a top of the first one of the second set of trenches and a second thickness at the bottom of the first one of the second set of trenches of between about 10 Å and about 20 Å.

10. A method of manufacturing a semiconductor device, the method comprising:
forming a first trench and a second trench within a substrate;
filling the first trench and the second trench with a first dielectric material layer;
removing at least a portion of the first dielectric material layer from the second trench, wherein after the removing at least the portion of the first dielectric material a bottom of the second trench is exposed;
implanting a first dielectric growth modifier into a first sidewall of the second trench at a first angle;
implanting a second dielectric growth modifier into a second sidewall of the second trench different from the first sidewall, wherein the implanting the second dielectric growth modifier is performed at a second angle different from the first angle; and
growing a gate insulator layer along a bottom of the second trench, the first sidewall, and the second sidewall, wherein the gate insulator layer has a first thickness along the bottom of the second trench that is less than a second thickness along the first sidewall and the second sidewall.

11. The method of claim 10 , wherein the dielectric growth modifier comprises fluorine.

12. The method of claim 10 , wherein the first angle is greater than an arctangent of a width of the second trench divided by a height of the second trench.

13. The method of claim 12 , wherein the second angle is greater than the arctangent of a width of the second trench and divided by a height of the second trench and opposite the first angle.

14. The method of claim 10 , further comprising depositing a gate electrode into the second trench.

15. The method of claim 10 , wherein the growing the gate insulator layer comprises an in situ steam generation process.

16. The method of claim 10 , wherein the growing the gate insulator layer comprises a chemical vapor deposition process.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a first opening and a second opening into a semiconductor substrate;
filling the first opening and the second opening with a dielectric material;
removing the dielectric material from the first opening without removing the dielectric material from the second opening;
performing an implant of dopants into a first sidewall of the first opening, wherein the performing the implant of dopants implants nitrogen;
growing a dielectric material on the first sidewall and a bottom of the first opening, wherein the presence of the dopants causes the dielectric material to grow at a different rate along the sidewall than at the bottom of the first opening.

18. The method of claim 17 , wherein the growing the dielectric material is performed at least in part by exposing the sidewall to steam.

19. The method of claim 17 , wherein the growing the dielectric material is performed at least in part using a chemical vapor deposition process.

20. The method of claim 17 , wherein the performing the implant of dopants is performed at a first angle that is greater than an arctangent of a width of the first opening divided by a height of the first opening.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ting Yu-Wei
• Tsai Chun-Yang
• Huang Kuo-Ching

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title