Integrated circuits having negative channel metal oxide semiconductor and positive channel metal oxide semiconductor

Patent metadata

Field	Value
Publication number	US-9099337-B2
Application number	US-201314089840-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Nov 11, 2009
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

An integrated circuit includes an NMOS and a PMOS disposed over a substrate. The NMOS transistor includes a first gate dielectric structure over the substrate, a first work function metallic layer over the first gate dielectric structure, a conductive layer over the first work function metallic layer, and a silicide layer over the conductive layer. The PMOS transistor includes a second gate dielectric structure over the substrate, and a second work function metallic layer over the first gate dielectric structure. The PMOS transistor is devoid of any silicide material on the second work function metallic layer.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an n-channel metal-oxide semiconductor (NMOS) transistor disposed over a substrate, the NMOS transistor comprising:
a first gate dielectric structure over the substrate;
a first work function metallic layer over the first gate dielectric structure;
a conductive layer over the first work function metallic layer; and
a silicide layer over the conductive layer; and

a p-channel metal-oxide semiconductor (PMOS) transi…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liu Chung-Shi
• Yu Chen-Hua

Classifications

• H10P30/20 Primary

  Electricity · mapped topic

• H10D64/01318

  Electricity · mapped topic

• H10D84/83135

  Electricity · mapped topic

• H10D84/85 Primary

  Electricity · mapped topic

• H10D64/667

  Electricity · mapped topic