Semiconductor device having dual work function gate structure, method for fabricating the same, transistor circuit having the same, memory cell having the same, and electronic device having the same

Patent metadata

Field	Value
Publication number	US-9634109-B2
Application number	US-201615337871-A
Country	US
Kind code	B2
Filing date	Oct 28, 2016
Priority date	Dec 16, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate in which a trench is formed;
a first impurity region and a second impurity region formed in the substrate separated from each other by the trench;
a gate electrode formed to fill a lower part of the trench; and
a capping layer formed over the gate electrode to fill an upper part of the trench,
wherein the gate electrode comprises:
a first work function liner formed over a bottom surface and lower sidewalls of the lower part of the trench, not overlapping with the first impurity region and the second impurity region, and is formed of titanium aluminum nitride;
a second work function liner formed over upper sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material; and
a low resistivity electrode fully filling the lower part of the trench over the first work function liner and the second work function liner,
wherein the low resistivity electrode is formed of a single layer.

2. The semiconductor device according to claim 1 , wherein the low resistivity electrode comprises:
a lower portion formed over the first work function liner to partially fill the lower part of the trench; and
an upper portion formed over the second work function liner to fill the remaining lower part of the trench, and having sloped sidewalls.

3. The semiconductor device according to claim 1 , wherein the low resistivity electrode includes a non-reactive material to the second work function liner.

4. The semiconductor device according to claim 1 , wherein the low resistivity electrode includes a fluorine-free material and is non-reactive with the second work function liner.

5. The semiconductor device according to claim 1 , wherein the low resistivity electrode includes titanium nitride.

6. The semiconductor device according to claim 1 , wherein the low resistivity electrode includes a reactive material to the second work function liner.

7. The semiconductor device according to claim 6 , wherein the gate electrode further comprises:
a barrier between the second work function liner and the low resistivity electrode, and between the first work function liner and the low resistivity electrode.

8. The semiconductor device according to claim 6 , wherein the gate electrode further comprises:
a first barrier between the first work function liner and the low resistivity electrode; and
a second barrier between the second work function liner and the low resistivity electrode.

9. The semiconductor device according to claim 8 , wherein the low resistivity electrode includes tungsten, and the first barrier and the second barrier include titanium nitride.

10. The semiconductor device according to claim 1 , wherein the second work function liner includes an N-type impurity-doped polysilicon.

11. The semiconductor device according to claim 1 , further comprising:
a bit line electrically coupled to the first impurity region; and
a memory element electrically coupled to the second impurity region.

Assignees

• Sk Hynix Inc

Inventors

• Oh Tae-Kyung
• Lee Jin-Yul
• Kim Eun-Jeong
• Kim Dong-Soo

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H01L27/2436

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L21/28088

  Electricity · mapped topic