Semiconductor device having dual work function gate structure, method for fabricating the same, transistor circuit having the same, memory cell having the same, and electronic device having the same

Patent metadata

Field	Value
Publication number	US-9508847-B2
Application number	US-201514739811-A
Country	US
Kind code	B2
Filing date	Jun 15, 2015
Priority date	Dec 16, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate in which a trench is formed;
a first impurity region and a second impurity region formed in the substrate separated from each other by the trench;
a gate electrode formed to fill a lower part of the trench; and
a capping layer formed over the gate electrode to fill an upper part of the trench,
wherein the gate electrode comprises:
a first work function liner formed over a bottom surface and lower sidewalls of the lower part of the trench, not overlapping with the first impurity region and the second impurity region, and formed of titanium aluminum nitride; and
a second work function liner formed over upper sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.

2. The semiconductor device according to claim 1 , wherein the first work function liner has a work function greater than the second work function liner.

3. The semiconductor device according to claim 1 , wherein the first work function liner has a high work function greater than a mid-gap work function of silicon, and the second work function liner has a low work function lower than the mid-gap work function of silicon.

4. The semiconductor device according to claim 1 , wherein the second work function liner includes an N-type impurity-doped polysilicon.

5. The semiconductor device according to claim 1 , wherein the gate electrode further comprises:
a first low resistivity electrode partially filling the lower part of the trench over the first work function liner; and
a second low resistivity electrode formed over the first low resistivity electrode to fill the remaining lower part of the trench over the second work function liner.

6. The semiconductor device according to claim 5 , wherein the second low resistivity electrode is a non-reactive material to the second work function liner.

7. The semiconductor device according to claim 5 , wherein the first low resistivity electrode includes a fluorine-free material and is non-reactive with the second work function liner.

8. The semiconductor device according to claim 5 , wherein the second low resistivity electrode includes a reactive material to the second work function liner, and the first low resistivity electrode includes a fluorine-free material and is non-reactive with the second work function liner.

9. The semiconductor device according to claim 5 , further comprising:
a fin region formed below the trench in which the first low resistivity electrode is formed.

10. A semiconductor device comprising:
a substrate in which a trench is formed;
a first impurity region and a second impurity region formed in the substrate separated from each other by the trench;
a gate electrode formed to fill a lower part of the trench; and
a capping layer formed over the gate electrode to fill an upper part of the trench,
wherein the gate electrode comprises:
a first work function liner formed over a bottom surface and lower sidewalls of the lower part of the trench, not overlapping with the first impurity region and the second impurity region, and formed of titanium aluminum nitride;
a second work function liner formed over upper sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material;
a first low resistivity electrode partially filling the lower part of the trench over the first work function liner; and
a second low resistivity electrode formed over the first low resistivity electrode to fill the remaining lower part of the trench over the second work function liner,
wherein each of the first low resistivity electrode and the second low resistivity electrode includes a material which is reactive with the second work function liner.

11. The semiconductor device according to claim 10 , wherein the gate electrode further comprises:
a lower barrier between the first work function liner and the first low resistivity electrode; and
an upper barrier between the second work function liner and the second low resistivity electrode.

12. The semiconductor device according to claim 11 , wherein the gate electrode further comprises:
an intermediate barrier between the first low resistivity electrode and the second work function liner.

13. The semiconductor device according to claim 10 , wherein the first low resistivity electrode and the second low resistivity electrode include tungsten.

14. The semiconductor device according to claim 10 , wherein the second work function liner includes N-type impurity-doped polysilicon.

15. The semiconductor device according to claim 10 , further comprising:
a fin region formed below the trench in which the first low resistivity electrode is formed.

Assignees

• Sk Hynix Inc

Inventors

• Oh Tae-Kyung
• Lee Jin-Yul
• Kim Eun-Jeong
• Kim Dong-Soo

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/027

  by etching at gate locations · CPC title