FinFET and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9634087-B1
Application number	US-201615239186-A
Country	US
Kind code	B1
Filing date	Aug 17, 2016
Priority date	Dec 30, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method is provided for fabricating a FinFET. The method includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate, wherein a position of the hard mask layer may corresponds to a position of subsequently formed fin; forming a doping region in the semiconductor substrate by using the hard mask layer as a mask to perform an anti-punch-through ion implantation process; forming an anti-punch-through region by performing an annealing process onto the doping region, such that impurity ions in the doping region diffuse into the semiconductor substrate under the hard mask layer; and forming a trench by using the hard mask layer as a mask to etch the semiconductor substrate and the doping region, wherein the semiconductor substrates between the adjacent trenches constitutes a fin.

First claim

What is claimed is:

1. A method for fabricating a fin field-effect transistor (FinFET), comprising:
providing a semiconductor substrate;
forming a hard mask layer on the semiconductor substrate, wherein a position of the hard mask layer corresponds to a position of subsequently formed fin;
forming a doping region in the semiconductor substrate by using the hard mask layer as a mask to perform an anti-punch-through ion implantation process;
forming an anti-punch-through region by performing an annealing process onto the doping region, such that impurity ions in the doping region diffuse into the semiconductor substrate under the hard mask layer; and
forming a trench by using the hard mask layer as a mask to etch the semiconductor substrate and the doping region, wherein the semiconductor substrates between the adjacent trenches constitutes a fin.

2. The method according to claim 1 , wherein:
an implantation angle of the anti-punch-through ion implantation process is in a range of approximately 0-10 degrees;
an implantation energy of the anti-punch-through ion implantation process is in a range of approximately 3-10 KeV; and
a dose of the anti-punch-through ion implantation process is in a range of approximately 1×10 14 -1×10 20 atoms/cm 3 .

3. The method according to claim 1 , wherein:
an annealing temperature is in a range of approximately 900-1300° C.; and
an annealing time is in a range of approximately 30 seconds-10 minutes.

4. The method according to claim 1 , wherein:
a width of the hard mask layer is in a range of approximately 10-50 nm.

5. The method according to claim 1 , wherein:
impurity ions implanted by the anti-punch-through ion implantation process are N-type impurity ions, or P-type impurity ions.

6. The method according to claim 5 , wherein:
the formed FinFET is an N-type FinFET; and
the impurity ions implanted by the anti-punch-through ion implantation process are P-type impurity ions.

7. The method according to claim 5 , wherein:
the formed FinFET is a P-type FinFET; and
the impurity ions implanted by the anti-punch-through ion implantation process are N-type impurity ions.

8. The method according to claim 1 , further including:
forming a shallow trench isolation structure, wherein a surface of the shallow trench isolation structure is below a top surface of the fin;
removing the hard mask layer;
forming a gate structure crossing and covering top and side surfaces of the fin; and
forming source and drain regions in the fins at both sides of the gate structure.

9. A method for fabricating a FinFET, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region;
forming a hard mask layer on the semiconductor substrate in the first region and the second region, wherein a position of the hard mask layer on the semiconductor substrate in the first region corresponds to a position of subsequently formed first fin, and a position of the hard mask layer on the semiconductor substrate in the second region may corresponds to a position of subsequently formed second fin;
forming a first doping region in the semiconductor substrate in the first region by using the hard mask layer on the semiconductor substrate in the first region as a mask to perform a first anti-punch-through ion implantation process;
forming a second doping region in the semiconductor substrate in the second region by using the hard mask layer on the semiconductor substrate in the second region as a mask to perform a second anti-punch-through ion implantation process, wherein a type of impurity ions implanted by the second anti-punch-through ion implantation process is different from a type of impurity ions implanted by the first anti-punch-through ion implantation process;
performing an annealing process onto the first doping region and the second doping region, wherein impurity ions in the first doping region diffuse into the semiconductor substrate in the first region under the hard mask layer to form a first anti-punch-through region, and impurity ions in the second doping region diffuse into the semiconductor substrate in the second region under the hard mask layer to form a second anti-punch-through region;
forming a first trench by using the hard mask layer on the semiconductor substrate in the first region as a mask to etch the semiconductor substrate in the first region and the first doping region, wherein the semiconductor substrate between the adjacent first trenches constitutes a first fin; and
forming a second trench by using the hard mask layer on the semiconductor substrate in the second region as a mask to etch the semiconductor substrate in the second region and the second doping region, wherein the semiconductor substrate between the adjacent second trenches constitutes a second fin.

10. The method according to claim 9 , wherein:
a P-type FinFET is formed in the semiconductor substrate in the first region, and a type of impurity ions implanted by the first anti-punch-through ion implantation process is N-type; and
an N-type FinFET is formed in the semiconductor substrate in the second region, and a type of impurity ions implanted by the second anti-punch-through ion implantation process is P-type.

11. The method according to claim 9 , wherein:
an N-type FinFET is formed in the semiconductor substrate in the first region and the type of impurity ions implanted by the first anti-punch-through ion implantation process is P-type; and
a P-type FinFET is formed in the semiconductor substrate in the second region and the type of impurity ions implanted by the second anti-punch-through ion implantation process is N-type.

12. The method according to claim 9 , wherein:
an implantation angle of the first anti-punch-through ion implantation process is in a range of approximately 0-10 degrees;
an implantation energy of the first anti-punch-through ion implantation process is in a range of approximately 3-10 KeV; and
a dose of the first anti-punch-through ion implantation process is in a range of approximately 1×10 14 -1×10 20 atoms/cm 3 .

13. The method according to claim 9 , wherein:
an implantation angle of the second anti-punch-through ion implantation process is in a range of approximately 0-10 degrees;
an implantation energy of the second anti-punch-through ion implantation process is in a range of approximately 3-10 KeV; and
a dose of the second anti-punch-through ion implantation process is in a range of approximately 1×10 14 -1×10 20 atoms/cm 3 .

14. The method according to claim 9 , wherein:
an annealing temperature is in a range of approximately 900-1300° C.; and
an annealing time is in a range of approximately 30 seconds-10 minutes.

15. The method according to claim 9 , wherein:
a width of the hard mask layer is in a range of approximately 10-50 nm.

16. The method according to claim 9 , further including:
forming a shallow trench isolation structure in the first trench and the second trench, wherein a surface of the shallow trench isolation structure is below top surfaces of the first fin and the second fin;
removing the hard mask layer;
forming a first gate structure crossing and covering top and side surfaces of the first fin;
forming first source and drain regions in the fins at both sides of the first gate structure;
forming a second gate structure crossing and covering top and side surfaces of the second fin; and
forming second source and drain regions in the fins at both sides of the second gate structure.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Xie Xinyun

Classifications

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L29/0638 Primary

  Electricity · mapped topic

• H01L21/2253

  Electricity · mapped topic

• H01L21/26513

  Electricity · mapped topic