Semiconductor packages including electrical insulation features

Patent metadata

Field	Value
Publication number	US-9634046-B2
Application number	US-201514685898-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	May 12, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A semiconductor package can include a substrate and a semiconductor chip inside the semiconductor package mounted on the substrate. A first conductive pattern can be on the substrate inside the semiconductor package and can be electrically connected to an input/output of the semiconductor chip. A holder can be on the substrate, where the holder can be configured to provide a recess in which the semiconductor chip is located. An electrically insulating adhesive layer can be configured to electrically insulate the first conductive pattern from an Electric Static Discharge (ESD) source located outside the semiconductor package and configured to adhere the holder to the substrate.

First claim

What is claimed:

1. A semiconductor package comprising:
a package substrate including a first conductive pattern;
a semiconductor chip mounted on the package substrate and electrically connected to the first conductive pattern;
a holder attached to the package substrate with an adhesive layer interposed therebetween and spaced apart from the semiconductor chip;
a transparent substrate attached on the holder and overlapping the semiconductor chip, wherein the adhesive layer contacts a side of the first conductive pattern; and
a second conductive pattern on the package substrate being spaced apart from and electrically insulated from the first conductive pattern,
wherein the adhesive layer contacts a side of the second conductive pattern that is directly adjacent to the side of the first conductive pattern.

2. The semiconductor package of claim 1 , wherein the package substrate comprises:
a substrate body where the first conductive pattern is disposed; and
a protective layer covering the substrate body and a portion of the first conductive pattern.

3. The semiconductor package of claim 2 , wherein a side of the protective layer is aligned with the side of the first conductive pattern.

4. The semiconductor package of claim 2 , wherein a bottom end of the holder extends between the first conductive pattern and the second conductive pattern.

5. The semiconductor package of claim 2 , wherein the protective layer comprises at least one groove exposing sides of the first and second conductive patterns, wherein the groove has a rectangular or bar form in plan view.

6. The semiconductor package of claim 5 , wherein the adhesive layer fills the groove.

7. The semiconductor package of claim 1 , wherein the semiconductor chip is an image sensor chip.

8. The semiconductor package of claim 1 , wherein a surface of the package substrate below a bottom surface of the holder has an uneven structure.

9. The semiconductor package of claim 1 , wherein the adhesive layer has an electrically insulating property.

10. A semiconductor package comprising:
a substrate;
a semiconductor chip inside the semiconductor package mounted on the substrate;
a first conductive pattern on the substrate inside the semiconductor package and electrically connected to an input/output of the semiconductor chip;
a holder on the substrate, the holder configured to provide a recess in which the semiconductor chip is located;
an electrically insulating adhesive layer configured to electrically insulate the first conductive pattern from an Electric Static Discharge (ESD) source located outside the semiconductor package and configured to adhere the holder to the substrate; and
a second conductive pattern laterally spaced apart from the first conductive pattern on the substrate, wherein the electrically insulating adhesive layer extends on the substrate from beneath the holder to the second conductive pattern.

11. The semiconductor package of claim 10 further comprising:
the second conductive pattern extending to outside the semiconductor package and exposed to contact with the ESD source.

12. The semiconductor package of claim 11 wherein a bottom surface of the holder is coupled to the electrically insulating adhesive layer.

13. The semiconductor package of claim 12 wherein the bottom surface of the holder extends over the first and second conductive patterns and bridges a separation between the first and second conductive patterns to define a groove.

14. The semiconductor package of claim 13 wherein the electrically insulating adhesive layer fills the groove between the first and second conductive patterns.

15. The semiconductor package of claim 10 wherein the electrically insulating adhesive layer is between a side wall of the substrate and a side wall of the holder.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jun Hyunsu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title