Formation of self-aligned source for split-gate non-volatile memory cell

Patent metadata

Field	Value
Publication number	US-9484261-B2
Application number	US-201414319893-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jul 5, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

First claim

What is claimed is:

1. A method of forming memory cells, comprising:
forming a conductive layer of material over and insulated from a substrate that has a first conductivity type;
forming a pair of spaced apart conductive control gates over and insulated from the conductive layer, wherein each of the control gates includes opposing inner and outer sidewalls, and wherein the inner sidewalls face each other;
forming a pair of first spacers of insulation material along the inner sidewalls and over the conductive layer;
performing an etch of the conductive layer to form a pair of floating gates of the conductive layer, wherein the floating gates include inner sidewalls that face each other and that are aligned with side surfaces of the pair of first spacers;
forming a pair of second spacers of insulation material each extending along one of the first spacers and along the inner sidewall of one of the floating gates;
forming a trench into the substrate, wherein the trench has sidewalls aligned with side surfaces of the pair of second spacers;
forming silicon carbon in the trench; and
implanting a material into the silicon carbon to form a first region therein having a second conductivity type.

2. The method of claim 1 , further comprising:
forming a block of insulation material over each control gate, wherein each of the first and second spacers extend at least partially along one of the blocks of insulation material.

3. The method of claim 1 , further comprising:
forming silicon dioxide and silicon nitride between each of the control gates and one of the pair of first spacers.

4. The method of claim 1 , further comprising:
performing an anneal process to diffuse the implanted material in the silicon carbon.

5. The method of claim 1 , further comprising:
forming an erase gate of conductive material disposed over and insulated from the first region.

6. The method of claim 1 , further comprising:
forming a pair of wordline gates each disposed adjacent to and insulated from one of the outer sidewalls and the substrate.

Assignees

• Silicon Storage Tech Inc

Inventors

• Su Chien-Sheng
• Yang Jeng-Wei
• Chen Yueh-Hsin

Classifications

• H10D84/0133

  Manufacturing common source or drain regions between multiple IGFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title