Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies

Patent metadata

Field	Value
Publication number	US-9633995-B2
Application number	US-201615050808-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	May 23, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

First claim

What is claimed is:

1. A method, comprising:
developing a bipolar transistor region on a substrate;
developing a metal oxide semiconductor (MOS) transistor region on the substrate and spaced apart from the bipolar transistor region;
depositing a polysilicon layer over the bipolar transistor region and the MOS transistor region; and
etching the polysilicon layer using a single mask to form:
a base above the bipolar transistor region; and
a gate shield above the MOS transistor region.

2. The method of claim 1 , wherein the MOS transistor region includes a laterally diffused metal oxide semiconductor (LDMOS) transistor region.

3. The method of claim 1 , wherein the MOS transistor region includes an extended drain metal oxide semiconductor (EDMOS) transistor region.

4. The method of claim 1 , wherein the MOS transistor region includes a vertical drain metal oxide semiconductor (VDMOS) transistor region.

5. The method of claim 1 , wherein the depositing the polysilicon layer includes epitaxially growing the polysilicon layer over the bipolar transistor region and the MOS transistor region.

6. The method of claim 1 , further comprising:
developing a buried layer on the substrate,
wherein the developing the bipolar transistor region includes developing the bipolar transistor region above the buried layer, and
wherein the developing the MOS transistor region includes developing the MOS transistor region above the buried layer.

7. The method of claim 1 , further comprising:
developing a body region within the MOS transistor region;
developing a drain well within the MOS transistor region and spaced apart from the body region; and
forming a gate structure above the body region, and the gate structure free of overlapping the drain well,
wherein the single mask defines the gate shield laterally above the gate structure and extending to partially overlap the drain well.

8. The method of claim 7 , further comprising:
developing a drain region within the drain well;
forming a gate electrode coupled to the gate structure; and
forming a drain electrode coupled to the drain region,
wherein the single mask defines the gate shield positioned between the gate electrode and the drain electrode.

9. The method of claim 7 , further comprising:
developing a drain region within the drain well;
developing a source region within the body region;
forming a source electrode coupled to the source region; and
forming a drain electrode coupled to the drain region,
wherein the single mask defines the gate shield positioned between the source electrode and the drain electrode.

10. The method of claim 7 , wherein the forming the gate structure is performed before the depositing the polysilicon layer and the etching the polysilicon layer.

11. The method of claim 1 , further comprising:
developing a body region within the MOS transistor region;
developing a drain well within the MOS transistor region and spaced apart from the body region;
developing a shallow trench isolation (STI) structure within the MOS transistor region and between the drain well and the body region; and
forming a gate structure above the body region, and the gate structure free of overlapping the drain well and the STI structure,
wherein the single mask defines the gate shield laterally above the gate structure and extending to partially overlap with the STI structure.

12. The method of claim 1 , further comprising:
forming a gate shield electrode coupled to the gate shield and configured to receive a shield bias voltage.

13. The method of claim 1 , wherein the polysilicon layer includes a P doped silicide material.

14. The method of claim 1 , further comprising:
forming a first deep trench isolation channel laterally surrounding the bipolar transistor region; and
forming a second deep trench isolation channel laterally surrounding the MOS transistor region.

15. A method, comprising:
developing a bipolar transistor region on a substrate;
developing a laterally diffused metal oxide semiconductor (LDMOS) transistor region on the substrate and spaced apart from the bipolar transistor region;
depositing a polysilicon layer over the bipolar transistor region and the LDMOS transistor region; and
etching the polysilicon layer using a single mask to form:
a base above the bipolar transistor region; and
a gate shield above the LDMOS transistor region.

16. The method of claim 15 , further comprising:
developing a body region within the LDMOS transistor region;
developing a drain well within the LDMOS transistor region and spaced apart from the body region; and
forming a gate structure above the body region, and the gate structure free of overlapping the drain well,
wherein the single mask defines the gate shield laterally above the gate structure and extending to partially overlap with the drain well.

17. The method of claim 16 , further comprising:
developing a drain region within the drain well;
forming a gate electrode coupled to the gate structure; and
forming a drain electrode coupled to the drain region,
wherein the single mask defines the gate shield positioned between the gate electrode and the drain electrode.

18. A method, comprising:
developing a bipolar transistor region on a substrate;
developing an extended drain metal oxide semiconductor (EDMOS) transistor region on the substrate and spaced apart from the bipolar transistor region;
depositing a polysilicon layer over the bipolar transistor region and the EDMOS transistor region; and
etching the polysilicon layer using a single mask to form:
a base above the bipolar transistor region; and
a gate shield above the EDMOS transistor region.

19. The method of claim 18 , further comprising:
developing a body region within the EDMOS transistor region;
developing a drain well within the EDMOS transistor region and spaced apart from the body region;
developing a shallow trench isolation (STI) structure within the EDMOS transistor region and between the drain well and the body region; and
forming a gate structure above the body region, and the gate structure free of overlapping the drain well and the STI structure, and
wherein the single mask defines the gate shield laterally above the gate structure and extending to partially overlap with the STI structure.

20. The method of claim 19 , further comprising:
developing a drain region within the drain well;
forming a gate electrode coupled to the gate structure; and
forming a drain electrode coupled to the drain region,
wherein the single mask defines the gate shield positioned between the gate electrode and the drain electrode.

Assignees

• Texas Instruments Inc

Inventors

• Babcock Jeffrey A
• Sadovnikov Alexei

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H01L21/32139

  Electricity · mapped topic

• H01L29/7816

  Electricity · mapped topic

• H01L29/66575

  Electricity · mapped topic

• H01L29/7835

  Electricity · mapped topic