Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies

US9306013B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9306013-B2
Application numberUS-201414286805-A
CountryUS
Kind codeB2
Filing dateMay 23, 2014
Priority dateMay 23, 2014
Publication dateApr 5, 2016
Grant dateApr 5, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: developing a bipolar transistor region on a substrate; developing a laterally diffused metal oxide semiconductor (LDMOS) transistor region on the substrate and spaced apart from the bipolar transistor; depositing an epitaxial polysilicon layer over the bipolar transistor region and the LDMOS transistor region; and patterning and etching the epitaxial polysilicon layer using a single mask to form: a base above the bipolar transistor region; and a gate shield above the LDMOS transistor region.

Assignees

Inventors

Classifications

  • using masks for conductive or resistive materials · CPC title

  • adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

  • the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title

  • using silicon technology, e.g. SiGe · CPC title

  • the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title

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What does patent US9306013B2 cover?
A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H10D84/401. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).