Multi-stack nanosheet structure including semiconductor device
US-2024023326-A1 · Jan 18, 2024 · US
US9306013B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9306013-B2 |
| Application number | US-201414286805-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 23, 2014 |
| Priority date | May 23, 2014 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.
Opening claim text (preview).
What is claimed is: 1. A method, comprising: developing a bipolar transistor region on a substrate; developing a laterally diffused metal oxide semiconductor (LDMOS) transistor region on the substrate and spaced apart from the bipolar transistor; depositing an epitaxial polysilicon layer over the bipolar transistor region and the LDMOS transistor region; and patterning and etching the epitaxial polysilicon layer using a single mask to form: a base above the bipolar transistor region; and a gate shield above the LDMOS transistor region.
using masks for conductive or resistive materials · CPC title
adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title
the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title
using silicon technology, e.g. SiGe · CPC title
the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title
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