Technique for fabrication of microelectronic capacitors and resistors

Patent metadata

Field	Value
Publication number	US-9633986-B2
Application number	US-201615175738-A
Country	US
Kind code	B2
Filing date	Jun 7, 2016
Priority date	Oct 31, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

First claim

What is claimed is:

1. A method of making an integrated electronic structure, the method comprising:
forming an array of trenches in a dielectric block on a substrate, a first portion of the array including wide trenches having a wide trench width and separated from one another by a first set of insulating columns, and a second portion of the array including narrow trenches having a narrow trench width and separated from one another by a second set of insulating columns;
preferentially lowering wall heights of the first set of insulating columns relative to those of the second set of insulating columns;
forming a first metal layer that fills the narrow trenches and partially fills the wide trenches, the first metal layer forming a metal serpentine resistor in a vertical orientation orthogonal to a plane of the substrate;
covering the first metal layer with an insulator;
thinning the insulator such that portions of the insulator present on top of the first set of insulating columns are preferentially thinned to a greater extent than portions of the insulator present between the wide trenches and a portion of the insulator present in the region of the narrow trenches; and
filling the wide trenches with a second metal layer, the second metal layer together with the first metal layer and the insulator forming a plurality of vertical and horizontal parallel plate capacitor antifuses, in the region of the wide trenches.

2. The method of making an integrated electronic structure according to claim 1 , wherein the preferentially lowering wall heights of the first set of insulating columns relative to those of the second set of insulating columns is carried out without a masking step.

3. The method of making an integrated electronic structure according to claim 1 , wherein the thinning the insulator is carried out without a masking step between the covering step and the filling step.

4. The method of making an integrated electronic structure according to claim 3 , wherein the thinning the insulator includes polishing the insulator for a fixed process time.

5. The method of making an integrated electronic structure according to claim 1 , wherein only two mask cycles are used from the forming an array of trenches step to the filling the wide trenches step.

6. The method of making an integrated electronic structure according to claim 1 , wherein the narrow trenches are characterized by a high aspect ratio in which each narrow trench has a wall height that is at least six times greater than the narrow trench width.

7. The method of making an integrated electronic structure according to claim 2 , wherein the preferentially lowering wall heights of the first set of insulating columns relative to those of the second set of insulating columns is carried out using a chemical mechanical planarization process.

8. The method of making an integrated electronic structure according to claim 1 , wherein the preferentially lowering wall heights of the first set of insulating columns relative to those of the second set of insulating columns is carried out using a touch clean process.

9. The method of making an integrated electronic structure according to claim 1 , wherein each insulating column in the first and the second sets of insulating columns has a same height.

10. The method of making an integrated electronic structure according to claim 1 , wherein each of the wide trenches and the narrow trenches has a height ranging from 100 nm to 100 nm.

11. The method of making an integrated electronic structure according to claim 1 , wherein the narrow trenches has a pitch of 32 nm or less.

12. The method of making an integrated electronic structure according to claim 1 , further comprising forming a first conformal metal liner on sidewalls and bottom surfaces of the wide trenches and narrow trenches and on top surfaces of the first set of insulating columns and the second set of insulating columns, wherein the first metal layer is formed on top of the conformal metal liner.

13. The method of making an integrated electronic structure according to claim 1 , further comprising planarizing the first metal layer to remove the first metal layer from top surfaces of the second set of insulating columns, while leaving a metal cap on each insulating column of the first set of insulating columns, wherein the insulator is formed on the metal cap and the second set of the insulating column.

14. The method of making an integrated electronic structure according to claim 1 , wherein the first metal layer comprises copper, gold, silver, titanium, aluminum, tungsten, platinum, tantalum or a combination thereof.

15. The method of making an integrated electronic structure according to claim 1 , wherein the insulator comprises silicon nitride carbide or an ultra-low-k dielectric oxide layer.

16. The method of making an integrated electronic structure according to claim 1 , further comprising forming a second conformal metal liner on the thinned insulator.

17. The method of making an integrated electronic structure according to claim 1 , wherein a top surface of the second metal layer is coplanar with a top surface of the portion of the insulator located in the region of the narrow trenches.

18. A method of forming thin and thick regions of an insulator without using a mask, the method comprising:
conformally depositing the insulator onto an irregular surface of a semiconductor substrate, wherein the irregular surface has a step structure having an upper step surface and a lower step surface connected by a sidewall; and
polishing the insulator for a fixed period of time using a chemical mechanical planarization process such that a portion of the insulator present on the upper step surface is thinned to a greater extent to a portion present on the lower step surface, wherein after the polishing the irregular surface remains covered by the insulator.

19. The method of claim 18 , wherein the irregular surface has a step height.

20. The method of claim 18 , wherein the insulator is a silicon nitride carbide material.

Assignees

• IBM
• St Microelectronics Inc

Inventors

• Zhang John H
• Clevenger Lawrence A
• Radens Carl
• Xu Yiheng
• Wornyo Edem

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title