Modular fuses and antifuses for integrated circuits

Patent metadata

Field	Value
Publication number	US-9240375-B2
Application number	US-201313931692-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Jun 28, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

First claim

The invention claimed is:

1. A microelectronic antifuse comprising:
an array of metal columns inlaid in a dielectric block so as to form a dielectric mesh network; and
a pair of electrodes, each electrode intersecting at least a portion of one row of the array of metal columns, the pair of electrodes arranged in parallel so as to form, together with the intersected metal columns, a pair of vertical capacitor plates, a resistance across the dielectric mesh network located between the pair of vertical capacitor plates encoding an on/off state of the antifuse.

2. The antifuse of claim 1 wherein the array of metal columns is arranged as a square matrix.

3. The antifuse of claim 1 wherein the array of metal columns is arranged as an offset matrix in which alternate rows of columns are offset from one another by a fixed distance to form a thin dielectric mesh network.

4. The antifuse of claim 1 wherein an antifuse voltage is determined in part by a volume of the metal columns.

5. The antifuse of claim 1 wherein an antifuse voltage is determined in part by a shortest distance separating the pair of vertical capacitor plates.

6. The antifuse of claim 1 wherein the metal columns that are not intersected by an electrode serve as dummy structures for a metal planarization process.

7. The antifuse of claim 1 wherein the row of the array of metal columns is programmably selected.

8. A microelectronic, antifuse comprising;
an array of metal columns inlaid in a dielectric block so as to form a dielectric mesh network; and
a pair of electrodes, each electrode intersecting at least a portion of one row of the array of metal columns, the pair of electrodes arranged in parallel so as to form, together with the intersected metal columns, a pair of vertical capacitor plates, a resistance across the dielectric mesh network located between the pair of vertical capacitor plates encoding an on/off state of the antifuse, an antifuse voltage being determined in part by a cross-sectional shape of the metal columns.

9. The antifuse of claim 8 wherein the metal columns are round cylinders.

10. The antifuse of claim 8 wherein the metal columns are square cylinders arranged in a diamond pattern.

11. A method of making a microelectronic circuit element, the method comprising:
forming a dielectric block;
patterning the dielectric block with an array of openings;
patterning the dielectric block with links to connect selected ones of the array of openings to form a geometrical shape;
filling the patterned array of openings and the links with metal; and
planarizing the array of openings,
wherein the patterning the dielectric block with links forms a pair of substantially parallel planes and the microelectronic circuit element is a capacitor suitable for use as a microelectronic anti-fuse.

Assignees

• St Microelectronics Inc
• IBM

Inventors

• Zhang John H
• Clevenger Lawrence A
• Radens Carl
• Xu Yiheng
• Wornyo Edem

Classifications

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title