Split ball grid array pad for multi-chip modules

Patent metadata

Field	Value
Publication number	US-9633914-B2
Application number	US-201514854553-A
Country	US
Kind code	B2
Filing date	Sep 15, 2015
Priority date	Sep 15, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.

First claim

What is claimed is:

1. A multi-chip module, comprising:
a substrate having a top surface and a bottom surface and containing multiple wiring layers, each of said multiple wiring layers having multiple wires, first pads on said top surface of said substrate and second pads on said bottom surface of said substrate;
a first active component attached to a first group of said first pads and a second active component attached to a second group of said first pads, wherein one pad of said second pads is a split pad having a first section and a non-contiguous second section separated by a gap, said first section connected by a first wire of said multiple wires to a pad of said first group of said first pads and said non-contiguous second section connected by a second wire of said multiple wires to a pad of said second group of said first pads, and wherein another pad of said second pads is a conventional pad having a contiguous top surface and a contiguous bottom surface;
a first solder ball in direct physical contact with said contiguous bottom surface of said conventional pad and connected to a next level of packaging under said conventional pad; and
a second solder ball in direct physical contact with said first and second sections of said split pad,
wherein said first solder ball has a first height in a first direction and said second solder ball has a second height in said first direction, wherein said first direction is perpendicular to said contiguous bottom surface of said conventional pad, and wherein said second height is sufficiently less than said first height such that said second solder ball is not connected to said next level of packaging.

2. The multi-chip module of claim 1 , further including:
a first set of wires of said multiple wiring layers directly connecting a first set of said first group of said first pads to a first set of said second group of said first pads;
a second set of wires of said multiple wiring layers connecting a second set of said first group of said first pads to a first set of said second pads;
a third set of wires of said multiple wiring layers connecting a second set of said second group of said first pads to a second set of said second pads; and
wherein said first active component includes first component pads attached to said first group of said first pads by solder bumps and said second active component includes second component pads attached to said second group of said first pads by solder bumps.

3. The multi-chip module of claim 1 , wherein said split-pad, including said gap, has occupies an area of said bottom surface of said substrate equal to the area of said bottom surface of said substrate occupied by said conventional pad having said contiguous top surface.

4. The multi-chip module of claim 1 , wherein an area of a top surface of said first section is greater than an area of a top surface of said non-contiguous second section.

5. The multi-chip module of claim 1 , wherein:
said first section has the shape of a first circular segment bounded by a first arc of a circle and by a first chord connecting the endpoints of said first arc;
said non-contiguous second section has the shape of a second circular segment bounded by a second arc of said circle and by a second chord connecting the endpoints of said second arc;
said gap defined the space between said first and second cord; and
a first radius of said first circular segment is the same as a second radius of said second circular segment, said first and second radius measured from the center of said circle.

6. The multi-chip module of claim 1 , wherein said first active component is a first integrated circuit chip and said second active component is a second integrated circuit chip.

Assignees

• IBM

Inventors

• Call Anson J
• Cohen Erwin B
• Minier Dany
• Sauter Wolfgang
• Stone David B
• Tremble Eric W

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/931

  Shapes of bond pads · CPC title